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Responder-4
- 4路抢答器,利用STC单片机设计出来的一个简单的四路抢答器-4 Responder, STC microcontroller design using a simple four out of Responder
VHDL-Responder-Course-Design
- 开始键按下后,8个进度指示灯依次点亮,之后开始抢答。4个按键开关代表4个抢答键,由数码管显示最先按下的开关序号,表示此号码抢答成功。若在进度灯全亮之前有任意键被按下,则表示有人犯规!系统结构描述:此系统共包括4个板块,分别是输入板块、计数器板块、数码显示器板块、判断板块,各功能组合一起构成一个完整的抢答器。-Start key is pressed, 8 progress lights were lit, and then answer in the beginning. 4 key switc
ad-transition
- AD转换资料...含文档和程序代码-Report of four Responder course design documents and program code with ...
quad-responder
- 四路抢答器,可供四名选手参加比赛的智力竞赛抢答。选手按下按键后,其他选手按下无效,同时对应的指示灯亮,蜂鸣器发出音响。由主持人控制指示灯和蜂鸣器复位。-Quad Responder, for four players to participate in quiz competition Responder. Press the key players, other players press the invalid, while the corresponding indicator light
Digital-Responder
- 数字抢答器① 用EDA实训仪的I/O设备和PLD芯片实现智能电子抢答器的计。 ② 智能电子抢答器可容纳4组参赛者抢答,每组设一个抢答钮。 ③ 电路具有第一抢答信号的鉴别和锁存功能。在主持人将复位按钮按下后开始抢答,并用EDA实训仪上的八段数码管显示抢答者的序号,同时扬声器发出“嘟嘟”的响声,并维持3秒钟,此时电路自锁,不再接受其他选手的抢答信号。 ④ 设计一个计分电路,每组在开始时设置为100分,抢答后由主持人计分,答对一次加10分,答错一次减10分。 ⑤ 设计一个犯规电路,对提
1234
- 四路抢答器,8051单片机开发,用C语言程序编写-Four Responder, 8051 Development, written in C language program
PIC--four-way-Responder-design
- PIC 16F877 应用程序:四路抢答器设计-Singlechip PIC procedures:four way Responder design
Four-intelligent-responder-
- 四路智能抢答器的VHDL实现,具有开始和复位功能,同时具有答题倒计时功能-Four intelligent responder VHDL implementation, with start and reset function, simultaneously has the answer countdown function
responder
- 实现四路抢答器功能,主持人可以控制抢答开始,也可以将各个抢答器清零-Responder function to achieve four-way, the host can control the answer in the beginning, you can also clear the various Responder
qidaqiFPGA
- Verilog 编写的纯逻辑四路抢答器,一位主持人控制按钮与四位抢答者控制按钮协同工作-Verilog prepared by the the Pure Logic Quad Responder, a moderator control button with four Responder the control buttons collaborative work
qiangdaqi
- 该文件是基于multisim设计的四人抢答器的仿真原理图-The file is a simulation-based the multisim design of four Responder' s schematic
slqdq
- 带有三十秒倒计时的四路抢答器。用multisim仿真的设计图。有一个主持人控制按钮,四个选手抢答按钮,还有一个复位按键-With thirty seconds countdown four Responder. With the the multisim simulation of the design. A host control buttons, four contestants answer button, and a reset button
shiyanqdq
- 基于FPGA 实现的4人抢答器模块的基础源程序。-FPGA-based realization of four Responder module
siweiqiangdaqi
- 基于stc89c51单片机的四位抢答器。-Based on 51 single-chip four Responder.
qdq
- 用VHDL语言实现四路抢答器功能,抢答之后不能再抢答,除非主持人按下复位键。可以显示四个选手分数,显示答题倒计时的时间,主持人可以控制加减分,分数通过显示屏显示。使用软件Quartus Ⅱ,可以将程序导入FPGA并能运行。有竞争模块,显示模块,分频模块,加减控制模块,计数器模块,蜂鸣器模块,译码模块,计分器模块,锁定模块等。-VHDL language with four Responder function can not answer after answer, unless the hos
four--people--qiangdaqi
- 基于fpga的多路抢答器 分为4路 有一路抢答后 其余按键将失灵 当主按键按下后 将正常运行-Fpga-based multi-channel Responder Responder is divided into four road all the way to rest after a failure when the main button to normal operation after the button is pressed
qiangdaqi
- 四人抢答器, 有4组抢答,系统开始后进入抢答状态,抢答开始后20秒倒计时,20秒倒计时后无人抢答显示超时,发出报警信号;当有一路抢答按键按下,该路抢答信号将其余各路抢答信号封锁,同时铃声响起,显示该路抢答台号;一轮结束后按复位键将所有状态复位。-Four Responder, Responder has four groups, the system begins to enter the answer in the state, began to answer in 20 seconds af
qdq
- 4人抢答,具有20秒倒计时报警清零机制,在线调试通过-Four Responder, with 20 seconds countdown alarm clearing mechanisms, online debugging
qiangdaqi
- 设计一个四路抢答器。抢答器必须具有互锁功能,同时抢答时每次只能有一个输出有效。同时,抢答时具有计时功能,限定选手的答题时间,在接近规定时间时进行提示,达到规定时间发出终止音。主持人可控制加分或减分。-Design a four-Responder. Responder must have the interlock function, while there can be only one answer when output is active. Meanwhile, the answer,
qiangdaqi
- 本程序为四路抢答器verlog HDL语言工程实例。-This program is four Responder verlog HDL language engineering examples.