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GF(2^8)
- 在网络安全编程中实现伽罗华域内两个数相乘-Programming is implemented in the network security domain Galois multiplying two numbers
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
Elliptic-Curve-Cryptography
- A brief algorithm to create ternary galois field of (3^x). through which large computation can be easily done.
RS
- RS纠错编码的原理介绍书籍。比较详细介绍了线性分组码、伽罗华域的概念，重要的是介绍了从原理至工程实现的设计方法。-RS error correction coding theory describes the books. A more detailed descr iption of the linear block code, the concept of Galois fields, it is important introduction to engineering design pr
GCMBlockCipher
- Implements the Galois Counter mode (GCM) detailed in NIST Special Publication 800-38D.
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
ghash_s390
- s390 implementation of the GHASH algorithm for GCM (Galois Counter Mode).
gf128mul
- An implementation of field multiplication in Galois Field GF(128).
musb-ux500
- GCM: Galois Counter Mode for Linux v2.13.6.
ghash-generic
- digest algorithm for GCM (Galois Counter Mode).
sh_ipmmu
- s390 implementation of the GHASH algorithm for GCM (Galois Counter Mode).
gf_calculator
- it is a gf (galois field) generator in C.
RLS_2
- L identi cation consiste à appliquer des signaux de perturbation à l entrée d un système (ceux-ci peuvent être de type binaire aléatoire ou pseudo-aléatoire, galois, sinus à fréquences multiples...) et en analyser la sortie dans le but d obtenir
CRC-generator
- 提出了一种32位并行和高度流水线的循环冗余码（CRC）发生器。 该设计可以处理5个不同的通道，每个输入速率为2Gbps（总输出吞吐量为5x4Gbps）。 生成的CRC与32位以太网标准兼容。 该电路已经在0.35Micron标准CMOS工艺中使用标准单元实现，其使用Galois Fields的特性，并且被认为是“自由的”IP。-A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is
program
- Built in self test to such that it generates non redundant inputs to tester using the concept of galois based primitive polynomial.
RS
- 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS
GF乘法器
- 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)