搜索资源列表
1024_FFT_IP
- 实现了1024点FFT的IP核,用起来很方便，直接调用即可-To achieve a 1024-point FFT IP core is easy to use, and can be called directly
Xilinx_FPGA_FFT_Application_Note
- Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！-Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port descr iption and specific settings as well as the source code for digital signa
STFT
- 短时傅里叶变换的FPGA实现零重复度使用了fft的IP核设计-When the Fourier transform of the FPGA to achieve zero repeatability using fft IP core design
fftip_1k
- FFT IP核调用 VHDL语言 quartus -FFT IP core VHDL language called quartus
FFTPVerilog
- FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
yinpinxinhaofenxiyi1233412
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核的基于FFT的音频信号分析仪-Based on Altera Cyclone II series FPGA embedded high-performance embedded IP core (Nios) soft core processor FFT-based audio signal analyzer
fft_ly
- 采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of
fft256
- 利用FPGA ip核实现256点的FFT转换，用vhdL语言实现。-Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.
fft_test
- ALTERA的FFT IP核时序的仿真，verilog语言。采用burst方式，FFT点数2048点-FFT IP core of timing simulation ALTERA, verilog language. Using burst mode, FFT points 2048 points
fft512_ipcore
- 512点的FFT 使用IP核 帮助新手理解-Using a 512-point FFT IP core to help the novice to understand
top_FFT
- 128k点流水FFT算法的IP核设计，顶层文件，一共13级流水-128k-point FFT algorithm running water IP core design, top-level file, a total of 13 water
fft_512
- 采用Xilinx提供的VHDL FFT ip核实现512点FFT，可以实现使能控制、时钟控制等功能-Using Xilinx provides VHDL FFT ip core to achieve implementation of 512 points FFT, with enable control, clock control and other functions
MyFFT
- 该程序可实现基于IP核的FFT算法，TESTBENCH用TEXTIO输入输出数据-The program can achieve FFT algorithm based on IP core, TESTBENCH based on TEXTIO input and output data
pipelined_fft_256
- pipelined fft/ifft 256 point ip core
fft_streaming
- 关于QuartusII FFT ip核的使用，采用Streaming模式，包含Modelsim仿真程序-About QuartusII FFT ip nuclear use, using Streaming mode, including Modelsim simulation program
mnl_avalon_spec
- Avalon-ST manual for FFT mega IP-core altera.-Avalon-ST manual for FFT mega IP-core altera.
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
UDP_Chat---Voice
- VS2010开发，通过网络UDP实时语音对讲，同时显示声音频谱，界面上可以设置IP地址音频采集参数，音频部分用windows音频底层API，频谱显示使用的FFT函数及Teechart绘图，使用时需要安装Teechart2012-VS2010 development, through the network UDP real-time voice intercom, also shows the sound spectrum, you can set the IP address of the a
fft_analyze
- 利用Altera的IP核，实现FFT算法使用信息流模式读写，使用SignalTap II嵌入式逻辑分析仪观察信号，A/D只要是并行的8位芯片都可以。-Achiving FFT by using Altera IP Core,you can observe the signal by the embedded logic analyzer Signal Tap II,as for A/D device, it s suitable for a parllarel 8 bits A/D device