搜索资源列表
StopWatch
- This a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.-This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
18B20
- verilog 写的18b20温度采集程序，并通过串品模块送出-verilog 18b20 uart ise
key
- PS2键盘协议代码 verilog，可以在ISE上跑，约束条件：NET"F50M" LOC="B8" NET"ps2_clk" LOC="R12" NET"ps2_data" LOC="P11" NET"rst" LOC="H13" NET"seg[6]" LOC="L18" NET"seg[5]" LOC="F18" NET"seg[4]" LOC="D17" NET"seg[3]" LOC="D16" NET"seg[2]" LOC="G14"
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
paobiao
- ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
gate4
- 运用verilog 语言编程，实现4输入逻辑门设计，利用ISE软件仿真，把程序下载到BASY2开发板上运行实现。-BASY2 engineered for ISE
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
adc0809
- ADC0809转换器的verilog版本,运用在ISE上，直接可用（注意没有考虑频道问题），结果显示在数码管里（十进制）-Verilog version ADC0809 converters, used in the ISE, directly available (note does not consider channel problems), the results are displayed in the digital tube (decimal)
inv_matrix
- 矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境-implement of inverse matrix
cordic
- cordic代码 verilog语言 产生三角波 适用在ISE上面-cordic code verilog language triangular wave generated above apply at ISE
turbo_encode
- turbo码的编码程序,verilog HDL,在ISE环境中-turbo code encoding process
Lab3_mux24a
- 4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
Lab5_x7seg
- 7段显示管的设计与实现.nexy3开发板。在2个7段显示管上显示一个2位的十六进制数，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
Lab6_decode38a
- 3-8译码器的设计与实现.3-8译码器的真值表，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3
S16_ADC
- 用Verilog HDL语言编写的AD转换器，可以再Xilinx芯片实现，用ISE软件环境下开发-Using Verilog HDL language AD converter, you can then Xilinx chip, with the ISE software development environment
yima
- Verilog语言描述38译码器功能，适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
cordic
- ise下用verilog实现的cordic算法的实现程序-ise under cordic algorithm verilog achieved with implementation of the program
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p