搜索资源列表
ModelSim_SE_6.1bkey
- ModelSim SE 6.1 (电子仿真)具体破解-ModelSim SE 6.1 (electronic simulation) Specific crack
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success
VHDL
- 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。
modelsim6.0
- modelsim使用教程6.0，详细介绍modelsim使用方法
4_in_1
- 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
Crack_ModelSim_SE_6.3d
- Modsim6.3 Crack and license
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
Digit_sys_proj-tbird
- T-bird LED by modelsim 6.5e
FPGA_ENVIRONMENT_BUILD
- FPGA环境的搭建，安装altera qaurtus ii 11.1和modelsim 6.5d se 图形化简单实用。-FPGA environment to build, install altera qaurtus ii 11.1 and modelsim 6.5d se graphically simple and practical.
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
ex1
- 设计一个循环灯控制器，该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。（假设外部提供频率为1MHz的方波信号） 编程环境为Quartus II 11.0 仿真环境为 Modelsim 6.6d 通过仿真可以看出。系统复位后，红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒，三个发光管循环发亮。 -Design a loop lamp controller that controls the red, green and ye
ModelSim-
- 此资料为modelsim使用教程6.0，包括初学者全套中文资料，为初学者提供很大帮组。-This information is modelsim tutorial 6.0, including a full set of Chinese information for beginners, providing great help group for the beginner.
Low-Error-and-Hardware-Efficient-Fixed-Width-Mult
- VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and m
sequence-detector
- 3比特的任意二值序列检测器，Quartus 10.0+modelsim 6.5SE联仿真报告形式-3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE，report forms
Programmable-filter-design
- 程控滤波器设计，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Programmable filter design,simulation with Quartus 10.0+ modelsim 6.5SE ， reports
Digital-frequency-meter
- 数字频率计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Digital frequency meter,simulation with Quartus 10.0+ modelsim 6.5SE ，reports。
display-circuit
- 计数显示电路 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Counter display circuit,simulation with Quartus 10.0+ modelsim 6.5SE， reports
detector-(1110010)
- 序列检测器（1110010）设计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE ， reports
MentorKG
- modelsim 6.5 crack license