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clock_0
- nios cpu test code this code was generated by altera tool automatically. You can obtain this code from the SOPC builder
tut_debug_software_verilogDE2
- This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.
tut_nios2_introduction
- This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor a
sourcefile
- 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序，希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序，对应四个按键，按其中任何一个键都可以发送一个中断； keyint.c是Nios中编写的C程序，用于检测按键的中断，如果检测到中断，会检测是哪个按键按下，从而执行相应的程序！ -In Altera' s Cyclone series FPGA development board interrupt key test
LCD-Drive-and-control-based-on-NIOSII
- 本文介绍了一种基于NIOS II软核处理器实现对LCD-LQ057Q3DC02控制的新方法。在设计中利用FPGA的Altera的SOPC Builder定制NIOS II软核处理器及其与显示功能相关的“软” 硬件模块来协同实现显示控制的软硬件设计。利用SOPC技术，将NIOS II CPU和LCD控制器放在同一片FPGA中，解决了通常情况下必须使用LCD 控制专用芯片才能解决LCD显示的问题。-This article describes an approach based on NIOS II
vhdl-MIPS
- Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
tt_nios_hardware_tutorial
- Altera NIOS II Hardware Tutorial
Avalon_uSequencer
- 用于控制Altera Avalon总线设备的一个微型的状态机，可以运行类似汇编语言的scr ipt，比Nios II CPU占用的资源少许多，可以生成明文的源代码-A tiny state machine used to control Altera Avalon bus devices. It can run scr ipt language similar to the assembly , occupied much less cells than the Nios II CPU res
71477225Nios
- altera nios对研究NIOS的人员很有帮助-altera nios research NIOS staff very helpful
55593396NIosII
- altera nios相关数据手册,对研究NIOS的人员很有帮助-altera nios data manual for the study of NIOS staff very helpful
GPS
- 基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project
LCDPS2
- 基于nios ii 驱动altera de1开发板上的lcd和ps2鼠标模块工程-based on the nios ii drive the lcd and ps2 module of altera de1 develop board
rf_wxtx
- 详细阐述了基于FPGA的RF无线通信技术的原理及硬件设计. 从系统的角度提出RF无线通信的完整设计方案,给出了基于Cyclone II芯片的Nios II的RF无线通信模块框图. 实验结果表明,采用ALTERA的Cyclone II芯片设计实现RF无线通信具有明显优势.-Detailed FPGA-based RF wireless communication technology theory and hardware design. From a system point of view p
crc_accelerator
- CRC 的Nios的软核处理，系统采用Altera Nios IP核进行CRC算法，算法运行时间比常规CRC校检节省很多。-CRC' s Nios soft-core processing, the system uses Altera Nios IP core for CRC algorithm, algorithm running time than the conventional CRC checkout save a lot.
tst_it
- Altera 测试 Interval Timer 的源码 在NIOS IDE下 调试通过-Altera Test Interval Timer source code to debug through the NIOS IDE
NiosII
- 设计了基于Altera的软核NIos处理器，为架构基于SOPC的片上可编程系统提供了方便-Designed based on Altera' s soft-core NIos processor for architecture is based on SOPC chip programmable system provides a convenient
DSO_Project
- 基于NIOS软核的示波器实现 硬件为ALTERA的飓风2待-DSO_Project for NIOSII
cyclone3_handbook.pdf.tar
- cyclone3手册 altera的nios -cyclone3 handbook nios ii
xapp460
- altera公司很有价值的技术文档，讲述了nios开发的一些技术问题-altera valuable technical documentation company, describes the development of some technical problems nios
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.