搜索资源列表
altera_maxII_PCI_Verilog
- Altera的MAXIICPLD模拟PCI接口的Verilog代码-Altera
PCI_BUS_ARBITER
- PCI仲裁器代码，用verilog硬件描述语言写的-PCI Arbiter code, written in verilog hardware descr iption language
pci_32tlite_oc
- 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
PCI9052
- 用verilog语言编译的pci协议实现，而且有具体的电路图-Compiled with the verilog language pci protocol implementation, but also the specific circuit
FPGA
- FPGA应用开发入门与典型实例 代码 FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。 -FPGA
PCIBridge
- pci bridge的verilog实现。-the verilog implemetion of PCI Bridge
LIP4331CORE_PCI
- PCI Peripherial Communication Interface BUS Verilog sourc code
PCIbus_Verilog
- PCI总线（Slave）接口FPGA的实现代码，全部为Verilog语言源码文件，还包括测试代码，内附设计实用说明文档。-PCI Bus (Slave) interface to FPGA implementation of the code, all source code files for the Verilog language, but also test the code, included the design and practical documentation.
PCI_Verilog
- Verilog 实现 PCI 转 LocalBus。已在Quartus 9.0下编译并且上PCBA验证通过。-Verilog achieve PCI to LocalBus. Has been compiled in Quartus 9.0 and verified by the PCBA.
verilog
- PCI/WISHBONE bridge Reference Design-PCI/WISHBONE bridge Reference Design
pci
- 实现pci接口，采用的是Verilog语言进行的编程-Realize the pci interface
mpci32-verilog
- 一个32BIT 33/66MHz PCI CORE，verilog 的RTL CODEs-pci ipcore writen by verilog
pci-board_latest.tar
- Its a source code for pci board in verilog language.
33M-(target)PCI-attice
- 32位33Mhz PCI接口程序设计参考，芯片是Lattice-This block is the top level Verilog module for the Vantis 32 bit 33Mhz PCI Target Reference Design.
PCI
- PCI总线仲裁参考设计Verilog代码，包括一些说明文件-PCI bus arbitration reference design Verilog code, including some documentation
data-Acquisition-by-PCI-
- 基于FPGA的PCI数据采集程序。PCI9054时序控制,开发语言verilog,开发环境quartus-FPGA-based PCI data acquisition program
PCI-MINI
- pci 32位33M的从设备接口的实现源代码，使用verilog语言设计的，对设计自己的pci软核很有参考价值。-pci 32 位 33M slave device interface source code, using verilog language design, the design of their pci soft core of great reference value.
Formal-Verication-of--the-PCI-Local-Bus
- Formal Verication of the PCI Local Bus Using Verilog-Formal Verication of the PCI Local Bus Using Verilog
pci
- pci总线的verilog描述，包含向量名定义，顶层设计等等的精确描述-usb clock verilog descr iption, including the vector name is defined, an accurate descr iption of the top-level design, etc.
PCI
- PCI协议代码,verilog 代码，前端实现