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AD4360config
- 此代码是ADI公司的锁相频率合成芯片ADF4360配置程序,采用Verilog HDL语言编程,并且经过实验验证。-This code is ADI PLL frequency synthesizer chip ADF4360 configuration procedures, using Verilog HDL language programming, and after experimental verification.
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法,(Verilog HDL)设计所需的模块有: (1)带PLL的全局时钟管理模块 system_ctrl_pll.v (2)OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig (3)OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 (4)SDRAM数据交互控制器Sdram_Control_2Port (5)VGA时序
Verilog_Ip_PLL
- 使用verilog 硬件描述语言编写的PLL调用程序,希望对大家有帮助!(Using Verilog hardware descr iption language written in the PLL call program, I hope to help you!)
TFT驱动显示
- 有verilog 编程语言,分为三个模块,包括pll锁相环,dispaly,以及driver模块