搜索资源列表
zhixinkeji
- 北京至芯科技FPGA的学习资料，从备战Quartus II安装到IIC通信协议，每一章都有Verilog代码并且可以实现仿真程序，非常好用，讲的很详细-Beijing Science and Technology FPGA to the core learning materials, preparing to install Quartus II IIC communication protocol, each chapter Verilog code and can achieve sim
led_display_design_8bitaddr
- 基于FPGA的8位LED自加显示电路，已在Quartus II上进行调试仿真，可在Cyclone IV系列板子上使用-FPGA-based 8-bit LED display circuit Canada, has been debugging simulation on Quartus II, can be used on board Cyclone IV series
2_CMOS_OV7725_Gray_Sobel
- 基于Quartus II 的灰度边缘检测源码，从输入端获取信息，可输出灰度边缘化图像，需要一定设备-Gray edge detection based on Quartus II source, obtaining information the input end, images can be output gray scale marginalized, need certain equipment
2_Mixer
- 基于Quartus II 13.0 的将两信号进行混合相乘的源码，适合于新人熟悉掌握该软件使用-Based on the Quartus II 13.0 mix two signal multiplication of the source code, suitable for a new master to use the software
3_FirFullSerial
- 基于Quartus II 13.0的FirFullSerial工程设计基本流程，内含详细doc文档-Based on Quartus II 13.0 FirFullSerial basic engineering design process, it contains a detailed doc document
text
- fpga锁相环实验——锁相环使用，开发环境为Quartus II -The fpga- phase-locked loop using phase-locked loop experiment, development environment for the Quartus II
Clock
- Quartus II 开发的多功能数字时钟，有计时、调时、闹铃、警报等功能-Quartus II muti-function Clock, function: timing, alarming, warning
333
- 课程设计设计主要使用了VHDL语言，采用的开发软件是Quartus-II，设计一个循环彩灯控制器和数字显示秒表。在Quartus-II开发平台下进行了编译、仿真。-Cycle lantern controller and digital display stopwatch
EDA
- 熟悉QuartusⅡ的Verilog HDL文本设计流程全过程，学习计数器的设计、仿真和硬件测试。-Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.
Altera_exercise
- this vhdl code for altera using quartus II v14 developed for beginners of altera fpga. if any comment or difficulty feel free to ask friends -this is vhdl code for altera using quartus II v14 developed for beginners of altera fpga. if any comment or
[1-1]初识驱动模块加载回调
- 驱动加载回调RIng0层，x64,X86不同实现，代码有话(Drive load callback, RIng0 layer, x64, X86 different implementations, code words)
CMI
- CMI编码原理图，可以通过对m5随即序列进行编码和解码(CMI is designed for m5 random list, which is should in the project, and it can decode it and get the original m5 list)
uart
- 嵌入式串口通讯，采用verilog编写，在altera开发板上运行(Embedded serial communication, written using Verilog, altera development board on the run)
fadder_1
- 利用quartus9.0编写的半加器程序，自己亲手设计，能有效运行出结果(Quartus9.0 prepared by the semi adder program, personally designed to effectively run the results)
hadder_1
- 用quartus9.0编写的一位全加器，自己设计，能有效运行出结果(Written in quartus9.0 with a full adder, their own design, can effectively run the results)
fadder_4
- 利用quartus9.0中元器件模块设计的四位全加器，能运行出结果(Quartus9.0 binary device using the design of four bit full adder, can run the results)
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器，亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
verilogiic1121
- tvp5150视频解码，平台quartus II(tvp5150 Video decoding,quartus II)
CCD_drive
- TCD1304 CCD 驱动 AD转 USB2.0传输(This code based on verilog language, worked on EP1C3T144 FPGA chip, developed on Quartus II 12.0 . The ccd's data transformed by USB2.0 after amplified and AD confromed.)
FPGA开发工具使用
- FPGA开发工具使用，介绍quartus ii 软件的安装与使用，具体的操作步骤详细阐述(FPGA development tools, This paper introduces the installation and use of Quartus II software, and expounds the detailed operation procedures)