搜索资源列表
Synchronous_read_write_RAM
- Synchronous read write RAM verilog。经过modelsim se仿真。
ram_sp_sr_sw
- Synchronous read write RAM verilog
verilog编写的ram
- verilog编写的ram
rom.rar
- 基于Verilog语言编写的各种只读存储器rom和随机存储器ram,Verilog language based on a variety of read-only memory rom and random access memory ram
dual_ram
- FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
dual_port_ram
- 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
VGA
- 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram
bubblesort1024ram
- 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking trad
using_the_block_RAM_in_Spartan-3_FPGA
- Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
ddpi_tx
- verilog语言编写的一个接口文件，使用乒乓ram-verilog language of an interface file, use the ping-pong ram
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
ProfiBus_Modbus_2008
- SPC3 PROGRAMS SP C3 PROGRAMS
VHDL
- 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY
profiles
- source code of counter,ram,lfsr etc
ShiftRegister
- Shift register verilog code
miffile
- 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
hh
- 双口RAM的verilog描述 双口RAM的verilog描述-Dual-port RAM of the verilog descr iption of dual-port RAM of the verilog descr iption
HardCamera
- The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable