搜索资源列表
RS_coder
- 基于verilog的RS编码器 绝对实用-Based on the RS encoder verilog absolute utility
ff_mul
- 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
RScoder
- 基于FPGA的RS编码器设计,verilog hdl语言。-RS encoder FPGA-based design, verilog hdl language.
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写,实现多周期CPU设计。能够完成以下二十二条指令。(均不考虑虚拟地址和Cache,并且默认为大端方式): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写,实现单周期CPU的设计。能够完成以下十六条指定: add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
rs_encoder_decoder
- RS编解码源程序,有详细的VERILOG程序,用于纠错-RS encoder and decoder
SAR_Send
- 对altera的RS编解码IP核进行仿真,并且写了编解码的控制模块,用verilog实现,通过仿真,编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core
RS_dec
- rs(204,188)译码器,verilog实现,乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way
RS_bmq
- 在QuartusII软件中用Verilog HDL编写的RS编码器的源代码-The RS encoder Verilog HDL prepared with in QuartusII software source code
rscode
- R S编 解 码 实 现 代 码 verilog语言-RS CODE AND ENCODE
rs_204_188----v1.0
- RS 编码和解码Verilog Code, 实现了RS(204,188)的编码和译码;-RS Coding and Decoding Verilog code, implement RS(204,188)
paobiao
- 本源码是用verilog编写的FPGA程序,其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
RS_enc
- RS编码器设计,使用Verilog实现。-RS encoder design, Verilog implementation.
rs_decoder_31_19_6.tar
- RS Decoder RTL verilog Code
RSdecoder
- 自己写的基于verilog的RS译码器,能够实现RS(240,224)码译码,一级流水设计,可连续译码也可非连续译码。-RSdecoder for RS(240,224).
Lab01
- verilog 入门练习,包括完整的Verilog实例,包括仿真的所有文件,主要是关于寄存器定义、名称映射、RS触发器定义等内容-verilog Getting exercises, including full Verilog examples, including all documents simulation, mainly on the register definition, name mapping, RS trigger definition, etc.
testbench.sv
- RS 编码和解码Verilog Code, 实现了RS(544,514)的编码和译码;--RS Coding and Decoding Verilog code, implement RS(544,514)
rsencoder.tar
- RS Encoder RTL verilog Code
RS_codeVerilog_program
- 运用verilog,实现了RS(255,247)的编码和BM算法的迭代译码,已通过仿真验证。-Using verilog, the RS (255,247) coding and the iterative decoding of the BM algorithm are implemented and verified by simulation.
基于FPGA的串口通信系统
- 该设计是基于 FPGA 的串口通信系统模拟仿真,通过对 RS-232 串行总线 接口的设计,掌握发送与接收电路的基本思路,并进行串口通信。采用 Verilog HDL 语言对 UART 波特率产生模块、数据发送模块、接收模块进行硬件描述, 再将其整合为一个 RS-232 收发模块,最终在顶层模块中将两个 RS-232 模块例 化,实现两块 FPGA 芯片全双工通信的设计。(Design of serial communication system based on FPGA)