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07_rs232_echo
- Controller RS232 in VHDL
RS232_TxD_source_code
- RS232 Transmitter VHDL Code
Rs232Rxd
- Rs232 Receiver VHDL code
VHDL
- 数码管显示，温度传感，红外感应，流水灯蜂鸣器，PS2,RS232的相关VHDL程序，已经在MAX-IIEPM570开发板上测试成功-Digital display, temperature sensor, infrared sensor, water lights buzzer, PS2, RS232 relevant VHDL procedures have been developed at MAX-IIEPM570 the success of on-board test
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
Rs232_Recv2
- controller RS232 for receiving serial data at different speeds
RS232_Controller
- This project is a RS232 Controller used to communicate two devices.
CameraDriver
- This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart interface
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
altera-schemic-
- FPGA应用，Altera的FPGA开发板原理图汇集，FPGA最小系统，rs232串口转换，VGA显示-FPGA applications, Altera' s FPGA development board schematic pooling, FPGA minimum system, rs232 serial converter, VGA display etc.
rs232
- 通过FPGA实现串口通信，结果在超级终端可见-Serial communication through the FPGA, the result can be seen in the HyperTerminal
screen_shoot
- Example of a screen shot module in a FPGA (upload bitmap file by RS232)
RS232_project
- 串口通讯 rs232 verilog程序，一次接受传送8bits-rs232 verilog project，reciver or trancimiter 8 bits onece
c_FPGA
- RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
UART
- A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
S7_PS2_RS232
- 基于verilog语言PS2接口和RS232接口的实现-PS2 based on verilog language interface and RS232 interface implementation
UP_IP_Library_80
- altera大学IP库，包含ps2、sdram、rs232等-altera University, IP libraries, including the ps2, sdram, rs232, etc.
CPLD_KEYBOARD
- 本设计是用VHDL语言来实现的基于RS232按位串行通信总线的行列式矩阵键盘接口电路，具有复位和串行数据的接收与发送功能，根据发光二极管led0—led2的显示状态可判断芯片的工作情况；实现所有电路功能的程序均是在美国 ALTERA公司生产的具有现场可编程功能的芯片EPM7128SLC84-15上调试通过的。该电路的设计贴近生活，实用性强，制成芯片后可作为一般的PC机键盘与主机的接口使用。 -The design is based on VHDL language to achieve
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx