搜索资源列表
DDRdesigen.pdf
- DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
Magnetic
- 磁珠专用于抑制信号线、电源线上的高频噪声和尖峰干扰，还具有吸收静电脉冲的能力。磁珠是用来吸收超高频信号，像一些RF电路，PLL，振荡电路，含超高频存储器电路（DDR SDRAM，RAMBUS等）都需要在电源输入部分加磁珠，而电感是一种蓄能元件，用在LC振荡电路，中低频的滤波电路等，其应用频率范围很少超过50MHZ。-Inhibition of signal lines dedicated to beads, the power line frequency noise and interfere
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
sdram
- its the stuff to know about ddr sdram
ddr_sdr_V1_1
- its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
JEDEC
- DDR SDRAM的JEDEC标准，对DDR SDRAM的编程学习者有帮助。-The JEDEC standards for DDR SDRAM, DDR SDRAM programming for learners help.
DDR_SDRAM_design_and_conclusion
- DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
XAPP200_ddr_sdram_64b
- Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
DDR-SDRAM
- 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to ach
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
400-Mbs-DDR-Controller
- 这个应用描述了怎样在Xilinx环境下，通过MIG实现DDR控制器-Synthesizable 400 Mbs DDR SDRAM Controller
SDRAM_DDR_DDR-II_Rambus_DRAM
- 内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM)-The principle and the timing of the memory (SDRAM, DDR, DDR-II, Rambus_DRAM)
DDR-with-CoolRunner-II
- 详细讲解了CoolRunner II CPLD与DDR SDRAM的接口设计-Explained in detail about the design of the CoolRunner II CPLDs and DDR SDRAM interface
DDR-SDRAM
- ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
DDR+SDRAM控制器verilog代码及中文说明文档
- DDR SDRAM控制器代码，不可多得的源代码。内附详细说明文档。
ddr-sdram
- It is complete document for DDR SD RAM program in verilog hdl
DDR-SDRAM-controller-verilog-code
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation