搜索资源列表
sIP__SPIIp
- spi总线的vhdl代码，试了了试能用。希望能对开发者有所帮助。 -spi bus vhdl code, try the test can be used. The hope is to help developers.
FLASH_read
- 对spi接口的flash操作，用VHDL语言实现，read控制，串行输入，可以1位、2位、4位读出-Spi interface on the flash operation, with the VHDL language, read control, serial input, to one, two, four read
TP2_SPI_source
- SPI Source VHDL language descr iption
AD7793
- 运用VHDL语言，实现AD7793芯片的采样程序和SPI的通讯程序，可以将该子模块加载到主程序中。-VHDL language to achieve the AD7793 chip sampling procedures and SPI communication program, this sub-module is loaded into the main program.
SDcard
- 一个能用SPI模式的SD读卡程序(VHDL)-A SD card reader program can use SPI mode (VHDL)
spi_slave_ctrl_rtl
- 从端SPI接口VHDL模块，以仿真通过-spi interface-----------------
SPI_Master_module
- 利用VHDL语言编写的SPI主机模块，采用内部自环回已经经过测试，发送接收数据正常，里面有modelsim工程，可以验证下仿真波形-SPI host module using VHDL language, has passed internal self-loopback test, sending and receiving data normally modelsim project, which can be verified under simulation waveforms
VHDL_SPI
- 很详细的SPI程序，VHDL代码写的。包含数据接收发送各部分代码。-SPI program, VHDL code written. Contain data transmission and reception of each part of the code.
xapp386
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Mas
xapp348
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunne
spi_final_presentation
- Implement SPI Master and SPI Slave cores (VHDL) Implement Master and Slave hosts (VHDL) Verify the entire design (SystemVerilog)
spi_test
- vhdl实现spi对M25P80flash进行操作。-vhdl realize spi on M25P80flash operation.
arcii_spi_001
- simple spi slave operating in mode 0 in VHDL.
quartus-file
- 利用VHDL编写SPI传输与接收协议，发送单字节信息，状态机思想-Use VHDL to write SPI transmission and receiving protocol, send a single-byte information, the state machine
SPI_MASTER
- VHDL实现的SPI Master 采用标准状态机，已完成实际验证-VHDL implementation of SPI Master standard state machine has completed the actual verification
SPI_verlog
- VHDL 语言实现的串转并 SPI 等等 实现-The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the master and the slave . Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. Whe
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
spi_slave_test
- SPI in VHDL originally designed for Spartan 3e
AD9511_spi
- 该代码为VHDL语言描述的AD7738 SPI通讯程序，包含一些重要注解-Thisis a serial communication promgram of AD9511 designed with VHDL which compared with some intercription.
AD9258_spi
- 该代码为VHDL语言描述的AD9258 SPI通讯程序，包含一些重要注解-This is a serial communication promgram of AD7738 designed with VHDL which compared with some discr iptions.