搜索资源列表
SlaveFIFO
- usb大全，第十八章实现slave FIFO数据传输的上位机程序源代码-usb Daquan, Chapter XVIII achieve slave FIFO data transfer PC source code
Keil
- USB大全第十八章实现slave FIFO的外部控制器程序-USB slave FIFO Daquan Chapter XVIII of the external controller to achieve program
FIFOGJ
- USB大全第十八章实现slave FIFO数据传输的固件程序源代码-Chapter XVIII Daquan USB slave FIFO data transfer to achieve the firmware source code
Bulkloop
- USB固件初始化，实现FIFO模式下地数据传输-USB firmware initialization to achieve data transfer FIFO mode Shimoji
USBDataAcquire_Instance
- 在CY68013的FIFO模式下实现FPGA从USB中获取数据-In CY68013 the FIFO mode the FPGA to get data from the USB
USB_FPGA
- 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
SFLASH
- FT2232L DUAL USB UART/FIFO I.C. FLASH TOOL
Apptest
- USB2.0 接收FIFO数据，下位机是CYC68013-USB 2.0 receive FIFO data
EbbulkloopZ
- EZ-USB FX2 SLAVE FIFO模式固件代码-EZ-USBB FX2 SLAVE FIFO mode firmware code -EZ-USB FX2 SLAVE FIFO mode firmware the code-EZ-USBB FX2 SLAVE FIFO mode firmware code
USB_Control_Firmware
- C++语言编写的针对CY7C68013A芯片的固件程序。包括了对USB Slave FIFO的配置和内部传输管道以及FIFO大小的必要控制。该程序在硬件上通过测试，在没有其他USB设备干扰的应用下，可以确保450Mbps通讯效率。-Firmware control for USB Slave FIFO in CY7C68013A. It define the necessary configuration on transaction segment and pipe as well as FI
FIFO_IN
- EZ-USB简单实现Slave FIFO工作模式。供初学入门~-EZ-USB is simple to achieve the Slave FIFO work mode. For beginner entry to
Cy7C68013-slavefifo-design.rar
- 使用Cypress的Cy7C68013A芯片进行设计，实现Slave FIFO模式的数据采集。程序包括USB固件程序以及主机程序。,Using Cypress' s Cy7C68013A chip design, data acquisition Slave FIFO mode. The program includes a USB firmware and host program.
61EDA_C2212
- 红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
usb_fifo_ft245b
- 基于FT245BM的FIFO接口设计 根据usb blaster改动-FT245BM FIFO interface design based on the changes under the usb blaster
EZ_USB_LOOPBACK
- 本程序：EZ-USB在slave fifo模式下，利用FPGA控制EZ-USB的数据读写-This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write
FX3-firmware
- application note focuses on the design of a synchronous FIFO master interface. A master initiates transfers, drives an address bus (if present), and usually supplies a clock to the slave. The slave device used in this design is another FX3 de
wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
FPGAluojidaima
- 16通道逻辑分析仪，100M，FPGA代码，包括FIFO，dram，usb等-16 channel logic analyzer, 100 m, the FPGA code, including FIFO, DRAM, usb, etc
FT245BL_test
- (1)FT245BL芯片datasheet(2)test，USB 转FIFO 芯片测试的verilog程序-(1) FT245BL chip datasheet (2) test, USB transfer FIFO chip testing procedures verilog