搜索资源列表
custom_mul
- vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier
cheng1.rar
- 用VHDL实现十六位移位乘法器 才有移位相加法来实现,Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
MULTI8X8
- 乘法器的硬件快速实现,采用Vhdl语言,对于学习芯片开发的人有用。-multiply is completed by vhdl.
Adaptive-digital-filter
- 自适应数字滤波器中乘法器的硬件设计,用VHDL语言实现自适应数字滤波器。-Adaptive digital filter in multiplier hardware design, using VHDL language adaptive digital filter.
multi8x8
- 该源码为8位乘法器的VHDL语言描述,由一个8位右移寄存器,2个4位加法器例化成8位加法器,一个16位数据锁存器构成。采用移位相加的方式,从被乘数的低位开始,与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit add
vhdl_123
- 几个简单的vhdl程序。包括加法器,减法器,乘除法等等。-A few simple vhdl program. Including the adder, subtractor, multiplication and division and so on.
multiplier.tar
- 用vhdl实现的booth算法乘法器,包含了multiplexer和rca adder,同时提供了一个测试文件,modelsim测试通过-Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass
mul
- 八位乘法器的VHDL程序,按照乘法的运算规则利用分支语句判断所有情况,最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
mult16s
- 16位乘法器,VHDL语言编写的,供大学交流学习-16-bit multiplier
8-bit
- 最基本的vhdl運算,採用8bit作乘法器,將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
Hardware_Multiplier
- 用VHDL写的硬件乘法器,以及测试过了,一个时钟周期内完成乘法运算。被乘数、乘数的宽度通过通用属性GENERIC参数改变而轻松改变,硬件除法器也快好了。-Written by VHDL hardware multiplier, and tested, and a clock cycle multiplication. Multiplicand, multiplier width parameter changes through the common property of GENERIC an
multi4_bsdu
- 用VHDL写的4*4乘法器,学习VHDL语言的可以-Use VHDL to write the 4* 4 multiplier, learning VHDL language can be
100vhdl_example
- vhdl语言的100个例子 VHDL语言100例 第1例 带控制端口的加法器 第2例 无控制端口的加法器 第3例 乘法器 第4例 比较器 第5例 二路选择器 第6例 寄存器 第7例 移位寄存器 第8例 综合单元库 第9例 七值逻辑与基本数据类型 第10例 函数 -VHDL language, VHDL language 100 examples of 100 cases of the first one cases of the control p
doc
- VHDL:用状态机的方法实现一个8位乘法器-VHDL: state machine method used to achieve an 8-bit multiplier
Mars_EP1C6F_fundemantal_demo
- FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。-FPGA development board source. Chips for the Mars EP1C6F.VHDL language. Can achieve some of the basic functions. Such as multiplier, adder, such as MUX.
Multiplexer
- 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
0
- 用vhdl语言实现4位乘法器,已被测试过,可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
cfq8
- VHDL语言编写8位乘法器非常实用语言绝对正确经过仿真的-VHDL language is very practical 8-bit multiplier is absolutely correct language after simulation
8-bit-Multiplier
- 一种基于加法器树方法的8为乘法器的VHDL源码,该方法虽然相对占有资源多,但仿真快-VHDLSourceProgramof8-bit-Multiplier