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95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
add
- 加法器的实现，用VHDL/FPGA/Verilog制作的实现的- adding machine use VHDL/FPGA/Verilog
yibanjiafaqidesheji-EDA
- 基于FPGA的快速加法器的设计与实现，在VHDL环境中波形图显示出结果，可以用二进制，十进制，十六进制表示 -FPGA-based fast adder design and implementation in VHDL environment, the results in the waveform display, you can use binary, decimal, hexadecimal
butterfly1
- FFT 蝶形处理器的VHDL代码，由一个加法器，一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
FPGA
- sin函数 交通灯 加法器的vhdl代码 自写，参考-sin function
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
multiply
- 四位加法器的VHDL代码，实现四位加法器FPGA实现。-Four adder VHDL code to achieve the four adder FPGA.
exp1
- 加法器，基于FPGA二进制的加法器，vhdl语言-Adder, FPGA-based binary adder, vhdl language
adder4_1
- 基于VHDL的四位加法器，运行环境quartus-VHDL-based four adder, operating environment quartusII
Adder-digital-display
- 基于FPGA的用VHDL程序编写的加法器数码显示程序-FPGA-based programming with VHDL adder digital display program
exp1.7_adder
- 用VHDL及verylog语言设计一个加法器，可以在Quartus II中仿真-Language Design with VHDL and verylog an adder, in the Quartus II simulation
BCD-adder
- 用VHDL语言设计一个BCD码加法器，输入A[3..0]、B[3..0],输出为SUM[4..0]。-bcd adder
eightbitadd
- 用VHDL语言实现8位的并行加法器，不同于行波进位加法器-8-bit parallel adder with VHDL, unlike the ripple carry adder
EDA_examples
- 此为四比特加法器，对于VHDL的初学者来说具有较大用途，运用的是ISE的开发软件，仿真结果正确。-This is four Bite Jia instruments used in, for the larger purpose of VHDL beginners, the use of the ISE development software, simulation results are correct.
1_ADDER
- ＣＰＵ内部的加法器用ｖｈｄｌ语言在可编程逻辑器件上的实现-Within the CPU is VHDL language addition in programmable logic devices for fulfillment
100vhdl
- VHDL语言100例，第1例 带控制端口的加法器，第2例 无控制端口的加法器等-VHDL language 100 cases, 1 case with a control port adder, two cases of the control port adder and so on. . .
jiafa
- 基于QUTER的VHDL言语的加法器设计-Based on the words of the QUTER VHDL adder design
Eight-parallel-adder
- 8 位并行加法器 vhdl 语言描述-Eight parallel adder
Desktop
- 四D触发器，最优先级编码器和加法器描述的VHDl文件-Four D flip-flop, the priority encoder and adder descr iption of the VHDl files
five
- 并入串出寄存器完成双向含异步清0和同步时钟使能的4位加法器的VHDL描述，并对其进行波形仿真，确定结果正确。- Incorporated into the string to the register to complete the two-way with asynchronous clear and synchronous clock so that the VHDL descr iption of the four adder energy and waveform simulatio