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100vhdl0621
- VHDL应用程序100例，适合初学者研究及练习 其中包含加法器译码器等多程序。-100 samples of VHDL, it is fit for beginner to study and practice. Adding machine, decoder and others are included.
数字系统设计相关
- 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
1_ADDER
- 这个是带输入的加法器vhdl代码,是带有输入端和进位的.-with imported Adder VHDL code, which is input into and spaces.
89_full_adder
- 这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.-into first place with the addition of VHDL code more complicated, just for reference.
booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to impr
VHDL
- 基本的VHDL程序代码，如加法器，乘法器，译码器，编码器等等，希望能给大家一些帮助，分享万岁！-Basic VHDL code, such as adders, multipliers, decoders, encoders, etc., I hope to give you some help, to share long live!
VHDL
- 设计五位逐级进位和超前进位加法器 练习使用EDA工具设计逻辑电路的方法-5bit adder
100-vhdl-examples
- 资料中包含了100个VHDL语言开发范例，如：加法器、乘法器、比较器、二路选择器、寄存器、综合单元库、函数、七值逻辑线或分辨函数-The data contains 100 examples of VHDL language development, such as: adder, multiplier, comparator, double-selection, register, comprehensive cell library, function, seven-value logic
VHDL
- 加法器、寄存器、半加器、译码器的硬件描述语言的描述-describe summator ，register，half adder,decoder with VHDL
vhdl
- vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的-vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on
add-based-on-vhdl
- 1位和4位加法器的VHDL硬件描述语言实现，可用quaturs实现。-add based on VHDL
VHDL
- 本程序包换一个游戏程序和各种功能的计数器和加法器源程序及波形发生器的代码程序，适合初学者使用-This program replacement a game program and a variety of functions counters and adders and waveform generator source code procedures, suitable for beginners
vhdl
- 通过VHDL语言，实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
2.1.5P4-Adder-VHDL-and-Waveform
- p4_adder 奔腾4cpu的加法器,包括carry selectadder carry generator -p4_adder Pentium 4cpu adder includes carry selectadder carry generator
VHDL
- 设计一个具有进位输入和进位输出的8位行波进位加法器-8-bit ripple carry adder design having a carry input and a carry output
D4W2adder
- 数码管动态显示VHDL代码。。。。。。。。。。(Digital tube dynamic display VHDL code)
adder8
- 基于vhdl的八位加法器，以两个四位加法器为基础(Eight bit adder of VHDL)
Half-Adder
- xilinx ISE平台提供1位半加法器，模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)
LAB
- SAM VHDL编码，包括数据选择器，加法器，简易逻辑电路，有限状态机等(FSM SAM ALU and many other different parts)