搜索资源列表
add
- 采用VHDL语言写的ADD加法器,并有原理图式-VHDL language used to write the adder ADD and the principle of schema
vhdl
- Very high speed integrated Hardware Descr iption Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Descr iption Language (VHDL)-
adder16b
- 潘松那本书上用vhdl语言描述的16位并入并处加法器-Pan book vhdl language used to describe the 16-bit adder into his
dds_first
- 用vhdl语言,通过加法器和寄存器实现fpga的dds功能-Using vhdl language, and register through the adder to achieve the fpga functional dds
mul
- 用VHDL语言实现十六位加法器(移位相加法)-VHDL language with Multiplier (Shift sum method)
lianxi
- 该程序是用VHDL语言实现一个四位整数的加法器代码-adder
test4adder
- 用VHDL实现的加法器,可以进行减法运算,运算结果通过数码管显示,由于设计时的按键较少,所以运算的范围比较小,只能计算64以内的加减法运算,可以作为学习资料来参考。-Adder using VHDL implementation can be carried out subtraction, calculation resulted in the adoption of digital tube display, due to the design of the keys relatively
testadder
- VHDL语言编写的加法器与测试代码,测试可用-Adder VHDL language and test code, the test can be used
jiajianfaqi
- 利用VHDL语言设计的两位加减法器,设计采用BLOCK并行设计可以同时进行加法与减法运算-VHDL language design using addition and subtraction of two instruments used, designed using BLOCK parallel design can be done concurrently addition and subtraction
adder
- 用vhdl实现加法器的功能,程序简介高效,移植性强-Vhdl adder with the realization of the function, procedures for efficient, portable and strong
ADDER
- VHDL语言的带控制端口的加法器,实现加法运算。-VHDL language, with a control port of the adder to achieve addition operation.
add
- 一个加法器,用VHDL写的程序,七位加法器,在V5的芯片上试过了-one adder
LIBRARYieee
- 顶·· ·· ·· ·· ·· ·· 用VHDL语言实现加法器设计 -Top with VHDL language Adder
example
- 我FPGA开发板的程序!!!包括数、码管iic、VGA、乘法器、串口。加法器、比较器、状态机等等等了,主要是VHDL的也有部分好似Verilog的。参考下吧-verilog...vga..uart...add...etc..
8adder
- 本实验示例中的8 位二进制并行加法器即是由两个4 位二进制并行加法器级联而成 的图13-4 所示的逻辑电路是由两个并行进位4 位加法器级联而成的8 位二进制加法 器-This is simple adder of 8 by VHDL.
chapter7
- VHDL 四位加法器 利用quartus II开发四位加法器,-VHDL comptur comparator_4
p4_adder.tar
- 用vhdl实现的P4加法器,包括主要元件rca加法器,carry select adder,pg模块,并提供了一个测试文件,用modelsim测试通过-P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test file, all modules have been teste
SHIFTER
- 使用VHDL语言编写的移位加法器,经过硬件实现通过-shifter
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab