搜索资源列表
usbsample
- 基于fpga和xinlinx ise的usb端口vhdl程序,希望对你有所帮助!-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
7seg
- 七段数码显示程序 VHDL 开发环境为Xilinx 的集成开发工具ISE-VHDL digital display program development environment for Xilinx ISE Integrated Development Tools
ISE_chinese
- 通俗的介绍了ise的使用方法,对vhdl和verilog开发的初学者来说是不错的选择-popular introduction to the use of the method ideally, the VHDL and Verilog development of the newcomer is a good choice
12864lcd_vhdl
- 12864图形点阵液晶驱动vhdl程序,用ise综合-12864 graphics dot-matrix LCD driver VHDL program, and ideally integrated
vgaCode
- VGA动画显示,用VHDL编程,用ise开发-VGA animation, VHDL programming, ideally with development
music_Code
- 音乐编辑与播放设计,采用VHDL编程,用ISE开发工具-music editing and playback design using VHDL programming, development tools with ISE
ps2_Code
- ps2接口编程实验,采用VHDL编程,用ISE开发工具-ps2 interface programming experiments using VHDL programming, development tools with ISE
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
ISE_uart
- 自己在ISE下用VHDL写的UART,简单,易懂-in ISE using VHDL was the UART, simple, understandable
UART(FPGA)
- 基于FPGA的串行通信UART控制器,采用VHDL语言编写,包含多个子模块。 在ISE或FPGA的其它开发环境下新建一个工程,然后将文档中的各个模块程序添加进去,即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new
usb(FPGA)
- 基于FPGA的usb程序,采用VHDL语言编写。 开发环境为ISE或者MAXPLUS2。-FPGA-based usb procedures, using VHDL language. Development Environment for the ISE or MAXPLUS2.
myUART
- 这是我用Xilinx公司的sparten3开发板,ISE集成开发环境,用VHDL语言开发的串口全双工通信程序,供大家参考,共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for
bujindianjiVHDL
- 步进电机定位控制系统VHDL程序与仿真波形.已经在xilinx ISE 8.1上验证.完全正确.-positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
sampleVHDL
- 采样等精度测量的VHDL程序..在xilinx ISE 8.1上验证通过-sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
DELAY1
- 本程序以ISE为开发平台,采用VHDL为开发语言,实现了对一个时钟信号延时的功能-the procedures to ISE for the development platform for the development of VHDL language, Implementation of a clock signal delay function
ClockDiv
- 本程序以XILINX公司的ISE8.2为开发平台,采用VHDL为开发语言,实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
decoder24
- 本程序以XILINX公司的ISE8.2为开发平台,采用VHDL为开发语言,实现了一个简单的译码器,适合处学者-the procedures to XILINX ISE8.2 for the development platform VHDL language for the development and achieve a simple decoder, the Department for scholars
TCNTL
- 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses
Freq_counter
- 本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以在较高速时钟频率(100MHz)下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真,并完成了综合布局布线,最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the
fifo_exp1
- 在ISE环境下用VHDL写的8*9FIFO