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SRAM
- 语言:VHDL 功能:利用VHDL编程,实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的,如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具:modelsim 综合工具:quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
I2C
- 语言:verilog 功能:用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路:一条串行数据线 SDA, 一条串行时钟线 SCL;串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s,快速模式下可达 400kbit/s ,高速模式下可达 3.4Mbit/s;在数据传输过程中,当时钟线为高电平时,数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化,会被认为是控制信号。 仿真工具:modelsim 综合工具:quartus -Language:
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
statemation-for-PWM-
- 基于状态机对步进电机的操作,利用VHDL语言编写,在Quartus 8.1环境下测试通过,可以建立波形文件做仿真实验-stepper motor based on ststemation
my_kmp_matching
- KMP算法的Verilog HDL实现,模式串从模块的外部输入,计算next函数,然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
VHDL-based-design-of-SPI
- 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境,以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外,该设计还实现了波特率发生器,数码管显示的功能。用DE2板实现具有电路简洁,开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述,从底层设计,分模块进行,充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
parallel-output-controller-(POC)
- 并行输出控制器,实现CPU与打印机之间的通信,程序基于VHDL语言,内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
cpu
- 一个简单的CPU设计,支持add,sub,mvi,mv四条指令,用Verilog语言编写,在Quratus II上编译通过,仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Pregunta01
- vhdl quartus maquina estados mealy vhdl quartus maquina estados mealy moore vhdl quartus maquina estados mealy moore vhdl quartus maquina estados mealy moore-vhdl quartus maquina estados mealy vhdl quartus maquina estados mealy moore vhdl quartus ma
FIR_IP_lowpass
- 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
lcd
- DE2-70开发板的LCD控制程序,能直接在DE2-70上运行。版本是quartus 9.0-DE2-70 development board of the LCD control procedures can be directly run on the DE2-70. Version of quartus 9.0
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制,其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
FM
- 在quartus ii下完成的用VHDL语言编写的数字式调频系统-Accomplished in quartus ii the use of VHDL language digital FM system
Sn_Quartus
- Synthesizerr frequency VHDL Quartus 90.
Signal-Generator-VHDL
- 这是基于quartus dds信号发生器设计的源程序-This is based on quartus dds source signal generator design
ADSP2011Local
- pci9054芯片本地总线控制示例程序,可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断,产生1,2,3等递增数据,配合pci9054驱动和应用程序完成数据传输 2.说明:文件夹内是Quartus 9.0的工程文件,使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at r
Quartus-II-10.1-Handbook--Volume-3
- design debugging of VHDL-the design of limited status in VHDL
i2c_master_slave_core_latest.tar
- IIC IP核,可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC,自定义II C IP核
dotdisplay
- 16*16点阵横向移动显示!采用QUARTUS II 9.0编译通过!-16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!