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100个vhdl设计例子
- 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Q
CPLDOGRAM
- 摘要: 文中介绍了数字频率计的结构、工作原理及计数方式，给出了基于VHDL语言的频率计系统的行为源描述，讨论了在VHDL的高级综合系统QuartusII的支持下，自顶向下地进行传输模块的设计工程，并给出了系统的仿真波形以及其应用实践。-Abstract : This paper introduces a digital frequency of the structure and working principle and counting, is based on VHDL Frequency
vhdl
- quartus 提示的各种错误问题的分析，和部分解决方案-quartus error analisyr
yuandaima
- FPGA多功能数字钟，描述语言VHDL，软件环境QuartusⅡ-FPGA multi-function digital clock, descr iption language VHDL, Quartus Ⅱ software environment
qiangda
- EDA课程设计智力抢答器 四路抢答器的设计以及程序和视屏 软件运行环境是：Quartus 9.1-EDA curriculum design intelligence Responder four answering device design and process and Screen software operating environment is：Quartus 9.1
0608190248xiatao
- 实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。 关键字：数字钟 闹钟 仿真 准点报时 -Quartus II software by means of experimental Lee designed a multi-functional digital clock and real
USBhpi
- USB FX2LP TO TI5402 HPI PORT MODE BOOT V1.0\FPGA代码(Quartus)-USB FX2LP TO TI5402 HPI PORT MODE BOOT V1.0 \ FPGA code (Quartus)
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
TEST5
- 8位硬件加法器设计 熟悉Quartus II的VHDL文本设计流程全过程，学习简单时序电路的设计、仿真和测试。-eight bit Hardware adder design Familiar with Quartus II VHDL text design flow process, learn the simple sequential circuits design, simulation and testing
Quartus-II
- Quartus II的使用教程包括Quartus II的软件教程，VHDL语言的编程方法，实际工程项目等。-Quartus II tutorial covers the use of Quartus II software tutorials, VHDL programming language, the actual engineering projects.
VHDL-and-QuartusII_975806262
- quartus及VHDL的人们学习资料，涵盖了VHDL所需的初步学习资料-People VHDL quartus and learning materials, covering preliminary VHDL learning materials required
VHD-L-QUARTUS--Counter
- 基于QUARTUS软件的VHDL语言开发，文件中含有VHDL语言设计的分频器，加法减法计数器，并生成有原理图，只要有QUARTUS软件即可仿真运行。-VHDL QUARTUS Counter
CPU
- 简单的CPU设计,使用VHDL 和 quartus ii 设计的cpu(a simply cpu design, vhdl quartus ii ,dsg gs h srh rsh rsh srjh srh)
基于Quartus-II-的FPGACPLD开发
- 基于Quartus-II-的FPGACPLD开发(Development of FPGACPLD based on Quartus-II)
FPGA实验指导书
- 很多程序实例，vhdl语言及quartus平台应用的实用实验资料(A lot of program examples, VHDL language and quartus platform application of practical experimental data)
VHDL程序
- 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)
VHDL方波
- 在Quartus II 中，利用VHDL 语言产生方波，程序如下(The VHDL language produces Fang Bo)
vhdl分频器设计
- vhdl分频器设计，用quartus软件偏写，可进行时钟的分频。(Design of VHDL frequency divider)
数电综合实验工程文件
- 像素鸟游戏代码，平台为quartus II，实现功能为简易像素鸟游戏。(Pixel bird game code)
VHDL模块
- 直接用模块就行了，加入到quartus里面即可(just use these modularities,then add these into your quartus)