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pwm-c
- 用VHDL编写的PWM控制程序，通过寄存器控制20余路PWM输出；qar是quartus的压缩包格式-VHDL prepared using PWM control procedures, through the registers to control more than 20 road PWM output qar is Quartus compressed packet format
Triangle_Wave_generater
- 采用vhdl语言编程，基于quartus平台的三角波仿真。-Using VHDL language programming, based on the Quartus triangular wave simulation platform.
200681556499797
- 曼彻斯特编解码 用vhdl编写的，经过quartus功能仿真测试过了的-Manchester codec prepared using VHDL, the Quartus functional simulation has been tested
dxxy
- 七位巴克码生成代码 用vhdl语言编写。将代码复制到quartus里面就可以用了-7 Barker Code generated code using VHDL language. Copy the code inside Quartus can use the
Pentium
- 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
Quartus7.2
- 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
VGAdisplay
- VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208-VHDL entry experiment. 256-color VGA display driver development software Quartus II 6.0 chip EP2c8Q208
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
PLLTEST
- Altera Quartus to Pll Source
lcdfinal
- LCD显示，用verilog写的，quartus-LCD display，verilog，quartusII
Saw
- Triangle generator in VHDL (Quartus).
Bramka_and
- Gate AND in VHDL (Quartus).
zad6_komparator
- Comparator in VHDL (Quartus)
zad6_multiplekser
- Multiplexer in VHDL (Quartus)
QuartusIIandModelSim
- 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation
QuartusII41_Installation
- 这是一个有关于VHDL的开发环境QUARTUS的安装方法的电子书。-This is a development environment on the VHDL Quartus installation method of e-books.
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
spi_vhdl_source
- SPI的VHDL程序，经过quartus验证的，不错！-SPI of the VHDL program, after verification quartus, yes!