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CF_Card
- CF卡的驱动程序 内附quartus功能模块-CF card driver included quartus function module
AD7656_Tri
- 触发AD7656进行双路采样的触发控制模块 内附QUARTUS生成的bsf文件-AD7656 Dual Trigger to trigger the control module sample included QUARTUS generated bsf file
fpgatri
- FPGA三态门的VHDL实现。包括2种不同的实现方法。编译环境是Quartus-VHDL 3-state gate FPGA implementation. Including two kinds of different implementations. Build environment is Quartus
FIFO
- 先入先出FIFO,用QUARTUS进行仿真-FIFO FIFO, the simulation with QUARTUS
HelloLED
- nios下实现helloled灯点亮 用vhdl语言编写 quartus环境实现-nios achieve helloled lamp lit environment with the vhdl language quartus to achieve
components
- quartus的几个IP核(PWM,RAM,I2C)-quartus several IP core (PWM, RAM, I2C)
frequenciometro
- Frequencimetro made whit vhdl on quartus work whit clk
DS18B20
- 8位单片机与DS18B20并行双向通信。 Quartus II 8.1项目工程文件. 主源程序文件为DS18B20.v,里面有详细注解。 例子: DS18B20 数据地址 0xf000(ROM=0) DS18B20 ROM指令地址 0xf001(ROM=1) 外部电源供电且只有一DS18B20的读取法: 发送CC到0xf001, 等待busy=0说明器件已准备好, 读0xf001的Bit1=1说明存在器件,Bit0=1为控制忙(可以省略此步) 发送44
Quartus
- 用vhdl编写的信号发生器源程序,可以产生正弦波,也可以根据需要产生其他波形-Prepared using vhdl source signal generator can produce sine wave, you can also produce other waveforms as needed
timer
- AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
PC
- 在quartus下实现了PC机的串口通信功能-The quartus achieve the PC-Serial communication function
jifei
- 在Quartus环境中,采用VHDL语言编写的出租车计费系统,系统共分为分频、状态切换、记程、计费等模块,模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imi
vhdl
- 抢答器的vhdl设计 设计任务: (1)设计一个可容纳4组参赛的数字式抢答器,每组设一个按钮,供抢答使用。 (2)抢答器具有第一信号鉴别和锁存功能,使除第一抢答者外的按钮不起作用。 (3)设置一个主持人“复位”按钮。 (4)主持人复位后,开始抢答,第一信号鉴别锁存电路得到信号后,由指示灯显示抢答组的编号,同时扬声器发出2~3秒的音响。 扩展功能: (5)设置一个计分电路,每组开始预制100分,由主持人计分,答对一次加10分,答错一次减10分。 计要求: (1
AlteraDMAdetector
- altera DMA代码控制器,开发环境为QUARTUS-altera DMA controller code, development environment for QUARTUS
UART
- 實作UART 介面 4 byte 傳送 或 4 byte 接收 開發環鏡 quartus 且 附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
Bufor
- Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
DHT22_v1.1
- 我以前曾发过V1.0版的,这是此版的修正版v1.1,修正了以前版本中的一个错误,即只能读一个数据后就再也读不出温度数据的错误。 这个是用Quartus II软件写的Verilog HDL语言写的与温湿度传感器DHT2x通信的代码. 里面有详细的注解. 主要用于DHT2x单线总线通信转换为8位并行总线通信,应用于具有外部8位总线访问功能的单片机直接读取温湿度数据. 此程序在EPM7128SLC-10中成功测试. -I' ve once spoke V1.0 version, whic
Stepper_controller_MAx
- stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog qu
Microprogramcontroller
- 微程序控制器部件实验,使用VHDL语言使用Quartus测试通过,模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU