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UART_final
- 利用vhdl硬件描述语言,模拟异步通用串行接口UART的通信方式,已在fpga上实际测试,通信性能不错,有一定的参考学习价值!-Using vhdl hardware descr iption language, simulated UART asynchronous serial interface common means of communication, the actual test in fpga, communication performance is good, there i
RS232-bus-protocol
- 有fpga VHDL原程序 锁脚文件 及下载文件 ,及uart通信协议-Fpga the VHDL program locks the foot of the original files and download files, and uart communication protocol
uart16750_latest[1].tar
- uart 16750 core discripe with VHDL language
RS232-Simple
- A simple UART example for reference in VHDL.
baud
- UART 异步通信串口协议的VHDL实现包括3个基本模块:时钟分频、接收模块和发送模块-UART asynchronous serial interface protocol VHDL consists of three basic modules: clock divider, the receiver module and transmit module
my_uart
- 使用VHDL描述的简单的串口通讯,在Quartus上验证过,包含所有文件-this is a simple uart
COMMAND232_SEND
- 这个代码用VHDL编写,是RS232在UART协议层发送数据的实现过程,很有用的!-The VHDL code is written, is the RS232 UART protocol layer in the implementation process of sending data, very useful!
FEP1C3_12_7_SP
- 基于FPGA的信号采集及频谱分析,用VHDL编写,压缩包里是Quartus下的工程。AD采样用状态机实现现,并存入LPM_RAM。设计了一个UART模块(也是状态机实现的),可将数据发到PC机上。 已通过测试。 -FPGA-based signal acquisition and spectrum analysis, using VHDL prepared compression bag Quartus engineering. AD sampling using the state mac
fifo
- VHDL 带FIFO的 UART 求大神帮忙修改-VHDL with FIFO UART pursuing big God help modify
12345
- 用vhdl编写的带fifo的uart,西电自动化系的作业-The vhdl write uart with fifo
uart_rx
- 用VHDL语言实现的Uart串口通信程序。在xilinx公司FPGA芯片验证过。-Uart serial communication program using VHDL. Validation in xilinx Company FPGA chip.
UART_VHDLCodes
- 基于VHDL的异步串口收发器,在FPGA上设计Uart接收模块实现从pc接收串口数据; 在FPGA上设计Uart发送模块,把从pc接收的数据的16进制值加1再发送给PC; 设计单片机和FPGA接口模块,把接收到的数据送给单片机,并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data desig
uart_lcd
- 基于FPGA的UART通信,并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行,证明此程序稳定可靠。时钟为50MHz,语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company product
1233
- 基于vhdl的uart设计论文,里面论述清楚,章节明白,具有参考价值-Uart vhdl-based design thesis, which discussed clearly understand chapters, a reference value
FPGA_UART
- FPGA实现UART串口通信协议 采用VHDL语言,顶层文件采用原理图的方式,简洁直观-FPGA Implementation of UART serial communication protocol
uart16750_latest.tar
- UART Module VHDL CODE TESTED ON FPGA
VHDLRS232Slave
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控 //制器,10个bit是1位起始位,8个数据位,1个结束 //位。串口的波特律由程序中定义的div_par参数决定,更改该参数可以实 //现相应的波特率。程序当前设定的div_par 的值是0x145,对应的波特率是 //9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 //划分为8个时隙以
uart_serial_vhdl
- fpga例程:用实fpga现uart串口通讯的vhdl详细代码,附一个串口通讯助手小插件-fpga routines: solid fpga vhdl now uart serial communication code in detail, with a small plug-in serial communications assistant
uart16750_latest.tar
- uart 控制器 verilog / vhdl 源代码-uart control verilog /vhdl source
fredivn
- UART的异步串口通信协议的VHDL语言实现 异步接收/发送模块-UART asynchronous serial communication protocol of the VHDL language to achieve asynchronous receiver/transmitter module