搜索资源列表
FIR_1
- FIR code in vhdl -FIR code in vhdl ----VVV
FIR
- 采用vhdl语言 设计FIR滤波器，经调试好使，献给广大硬件开发的朋友参考学习-FIR filter design using vhdl language, so that upon commissioning, the development of friends dedicated to the general hardware reference learning
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
FIR-LOOP-
- 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
fir-filter
- fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
fir4
- 基于vhdl的长度为4的fir滤波器，经过官方软件认证-Based on the length of 4 vhdl fir filter, after the official software certification
FIR
- This FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit-This is FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
26352153-VHDL-Coding-for-FIR-Filter
- VHDL filter design powerpoint
FIR---ALEX
- Filter c language, better validation, able to run the filter C language-FIR filter VHDL, you can use, though a bit......
VHDL
- 这个是基于一下的要求设计的：1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。-This is based on what the requirements of the design: an input and output data width is 12, 2, the order of the four stages of linear phase FIR filters, 3, type: low pass
designing-of-FIR-filer-based-on-FPGA
- 该文件是基于FPGA设计FIR滤波器设计的VHDL语言代码。-designing of FIR filer based on FPGA
FIR
- an FIR code which is writen in vhdl. this entity has clk and reseet inputs, and the filter output is provided as well. the coefficients of the filter are passed using a set of constants.
FIR
- fir数字滤波器，VHDL语言编程，先通过MATLAB计算得到参数。-fir digital filter VHDL language programming, first obtained by MATLAB calculated parameters.
fir
- 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
fir
- 该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用-design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language.
fir
- 本历程是用 VHDL实现fir滤波器cds算法的历程，熟悉CDSsuanfa -This process is to achieve fir filter algorithm cds course, familiar with CDSsuanfa
FIR-filter-vhdl
- FIR数字滤波器设计，用VHDL来实现，用quarsII软件实现其功能-FIR FILTER vhdl
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
fir-ip-vhdl
- altera quartus fir ip核 vhdl程序 含测试文件-altera quartus fir ip nuclear vhdl program including test files