搜索资源列表
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
VGADIY
- 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
uart_tran
- UART串口的传送verilog原程序，已经经过了编译仿真-Verilog UART serial transmission of the original procedure has been compiled after a simulation
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
c20_cordic_computer
- 精通verilog HDL语言编程源码之6--CORDIC数字计算机的设计-Proficient in language programming verilog HDL source of 6- CORDIC digital computer design
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
Verilog
- verilog的基础知识，可供初学者参考-basic knowledge of Verilog for beginners and reference
seg7led
- Verilog HDL源码，显示器段数码管数字累加，测试通过-Verilog HDL source code, the display segment digital tube digital cumulative, testing through
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
traffic
- 模拟交通灯 verilog CPLD EPM1270 源代码-Simulation of traffic lights verilog CPLDEPM1270 source code
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
4weishuzipinlvjikongzhimokuai
- Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
fir
- 本设计用verilog代码实现FIR滤波器！-Verilog code of the design FIR filters to achieve!
median
- 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
ldpc_decoder_802_3an.tar
- 802.3an Ethernet 以太网络 LDPC Verilog 网表实现-802.3an Ethernet Ethernet LDPC Verilog netlist to achieve
hdb3_1.1
- verilog 语言hdb 3 编 码 经过测试，但冗余问题未解决-Verilog language coding hdb 3 tested, but unresolved questions redundancy
risc8
- PIC单片机的verilog实现，不记得在哪里下载的。源文件中应该有的。-PIC MCU Verilog realized, can not remember where to download. Source file should have.