搜索资源列表
sdram_mdl
- FPGA控制SDRAM的工程，是用Verilog写的，很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
Tuart_tx_rxh
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 -The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC sponta
FA161_LCD_display
- 联华众科FA161的开发板上实现LCD显示的一个工程文件，编程语言Verilog。可以在LCD上显示按键值。-Lianhua Zhongke FA161 development board LCD display, a project file, programming languages Verilog. The key values can be displayed on the LCD.
RS232
- RS232与电脑串口的通信控制代码，verilog hdl代码，里面包括完整的ISE工程-RS232 and computer serial communication control code, verilog hdl code, which includes a complete ISE works
PC
- Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。-Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.
multiplier_interface
- verilog 写的工程，是个基于流水线的乘法器-verilog write the works, is based on a pipelined multiplier
mean
- 自己做的一个计算均值的verilog代码，一个工程，共大家参考-Own a verilog code to calculate the mean, a project, a total of reference
led
- quartus 工程 测试硬件LED Verilog 源码-the quartus engineering test the hardware LED Verilog source
a-simple-state-machine
- 简易状态机 verilog实现的简单状态机，全工程不错的 典型历程 值得学习入门很好的实验例程-Simple state machine verilog achieve a simple state machine, the typical course of the whole works good deserves learning entry good experimental routines
AD9957_Signal_Generate
- AD9957芯片通过FPGA配置的verilog程序,要自建工程，代码测试完全可用-AD9957 chip FPGA configuration verilog program, to be self-built project, code test is completely available
dual ram
- 此文件是FPGA工程文件，包含了dualram的设计代码和testbench代码，使用了verilog hdl编写，仿真结果符合设计要求。
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
fdivision
- 一个分频的quartus工程，用verilog写的，改变i的值可以实现任意分频，绝对原创-Quartus project a divide verilog write, change the value of i can achieve arbitrary divide absolute originality! ! !
median_filter
- 中值滤波的verilog实现，完整工程，调试通过-Median filter verilog achieve complete engineering, debugging through
Quartus_II-training-file
- Quartus 培训和使用教程，包括使用原理图输入，使用Verilog建立工程等-Quartus training file，include usingthe schametic to create project,and use the verilog file to create the project.
LAB-2
- 用FPGA实现对VGA的控制，没有用到niosII,只是用硬件描述语言verilog。整个工程。-With FPGA VGA control is not used niosII, just verilog hardware descr iption language. The entire project.
LAB-16
- 用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
AD5300
- DAC AD5300的verilog驱动,整个工程，亲测好用。-verilog code for AD5300 DAC.
Matrix_Keyboard
- Verilog编写的4x4矩阵键盘扫描代码，可用QurtursII直接打开工程。具体实现的功能为按下按键，数码管可相应显示0、1、...E、F-Verilog prepared 4x4 matrix keyboard scan code and it s directly available in QurtursII . The concrete realization of the function: key is pressed, the digital tube to the corres
SinPout
- FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output