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sim.rar
- 通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真,Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
Hamming_Decoder
- (7,4)Hammming码解码器，verilog代码实现。监督矩阵为HT=[1,0,0 0,1,0 0,0,1 1,0,1 1,1,1 1,1,0 0,1,1]-(7,4) Hammming code decoder, verilog code. Monitoring matrix HT = [1,0,0 0,1,0 0,0,1 1,0,1 1,1,1 1,1,0 0,1,1]
mp3_decoder
- MP3解码的VHDL实现，包括霍夫曼解码等-VHDL realization of MP3 decoding, including Huffman decoding
state
- 米勒解码器的状态转换模块。用verilog语言编写，ISE为开发环境-Miller decoder module of the state transition
out
- verilog语言编写的米勒解码的输出模块加仿真波形正确了-Miller verilog language decoder output waveform simulation module plus correct
2_to_4_decoder
- a 2_to_4 decoder example in verilog.
t4
- Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
2x4_decoder
- 2*4 decoder program in verilog
Sevenseg
- verilog code for a decoder that converts bcd to seven segment leds
encoder8_3
- 用VERILOG语言实现了常用8_3编码器.-Verilog language used to achieve a common decoder 3-8.-With the VERILOG language to implement common 8_3 encoder .- Verilog language used to achieve a common decoder 3-8.
2
- simple code of some kind of base decoder based on verilog
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
ptos
- 16位并行转串行译码器Verilog，以及synopsis综合结果，行为级、门级网单，均已通过仿真验证-16bit parallel to serial decoder and aynthesis result
binary_to_BCD
- 将二进制码转换成BCD码，在verilog环境下可以封装为译码器-BCD code into the binary code in verilog environment is encapsulated as decoder
haiming
- 信息论与编码中，实现的一个简单的（7,4）系统线性分组码，也即海明码-Construct a systematic (7,4) linear block code.You can use c lauguage or HDL (VHDL or Verilog-HDL) to describe it. Construct a linear block decoder,and decode the received code vector[0 1 0 1 1 0 1].Please write the
decoder3_8
- 这是个三八译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder 38, which the program is written in VERILOG, it is suitable for beginners
decoder38
- 这是个译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder, which the program is written in VERILOG, it is suitable for beginners
Solomon
- Solomon Decoder in verilog
8
- 利用verilog HDL编程驱动七段译码显示器，显示一位8进制变化。-Using verilog HDL programming seven segment decoder display driver, display an 8-ary change.
decoder4to16
- this is a verilog code for 4 to 16 decoder