搜索资源列表
decod4_16_with_decod3_8
- 4to16 decoder with 3to8 decoder verilog code-4to16 decoder with 3to8 decoder verilog code!!
haming-code
- 4to16 decoder with 3to8 decoder verilog code-4to16 decoder with 3to8 decoder verilog code!!
Verilog_Decoder
- Decoder are designed to the case statement to minize the coding and computation time for a decoder operation in verilog module.
decoder_case
- verilog hdl program for decoder
decode810
- 使用硬體描述語言verilog 的 8b10b-a 8b10b decoder use verilog
Lab3
- This is stopwatch writen in Verilog HDL. Also there is code for 7-segment display decoder. I tested it on ALTERA de2-115 development and education board.
decode3to8
- 一个简单的3-8译码器，verilog语言文件-Simple 3-8 decoder, Verilog language
S1_38yima
- 3-8译码器的verilog HDL代码，是红色飓风EP1C6开发板上的一个基础学习的范例。-3-8 decoder Verilog HDL code, is a basic study of the red hurricane EP1C6 development board example.
Seg7decode
- verilog HDL的7段数码管译码代码，可以使用-7 segment LED decoder with verilog HDL
fpga-jpeg
- JPEG硬件解码器设计 verilog实现-JPEG hardware decoder design verilog implementation
viterbi_decoder_axi4s
- Viterbi译码器的verilog代码和测试-Verilog code and testing of the Viterbi decoder
S1_38YIMA
- 掌握 verilog 语言的设计输入，编译，仿真和调试过程；实验主要实现一个 3/8 译码器。-Master verilog language design entry, compilation, simulation and debugging process experiment to achieve a 3/8 decoder.
aaa
- 用verilog vhdl 编写的 38译码器，包括源代码和测试模块-38 decoder
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写，ISE为开发环境 ，经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
decoder_38
- 38译码器，用verilog hdl 编写-38 decoder, written in verilog hdl
Verilog_Project_INSTRUCTION_DECODER_GROUP_10.tar.
- Verilog code on Instruction Decoder of 8085
rs_encoder_decoder
- RS编解码源程序，有详细的VERILOG程序，用于纠错-RS encoder and decoder
code_83
- 3-8译码器的verilog程序实现-3-8 decoder verilog program ..............
LIP1754CORE_risc16_decoder
- LIP1754 RISC16 Decoder verilog source code.
LIP1756CORE_dsp32_decoder
- LIP1756 DSP32 Decoder verilog source code.