搜索资源列表
LCD.基于FPGA的LCD1602驱动
- 基于FPGA的LCD1602驱动，verilog代码，已经调试成功,LCD1602-driven FPGA-based, verilog code debugging has been successful
S8_VGA.VGA显示接口的verilog控制程序
- VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动,VGA display interface Verilog control procedures. Control for VGA display driver
(fpga)sdram.rar
- verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
sram读模块基于FPGA的实现
- sram读模块基于FPGA的实现 verilog源代码,sram
verilog.rar
- 《数字信号处理的FPGA实现》（第二版）光盘verilog代码," The FPGA digital signal processing to achieve" (second edition) CD-ROM code verilog
FFT_16.rar
- FFT快速傅立叶变换-verilog，基于verilog的FFT源码，QuartusII上仿真通过,FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation
HPI.rar
- 基于CPLD/FPGA器件的HPI接口程序 难能可贵,HPI based on CPLD/FPGA instrument
tftlcd.zip
- TFT LCD controller verilog code using ALTERA FPGA.,TFT LCD controller verilog code using ALTERA FPGA.
DDS.rar
- FPGA控制AD9854的源文件，verilog，附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
verilog-PS2.rar
- 在FPGA内，实现PS2键盘数据读取功能，verilog源代码,In the FPGA, achieving PS2 keyboard data read functions, verilog source code
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
FPGA_SDRAM_PCI
- 一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
Verilog-pci
- PCI的FPGA实现，使用verilog硬件描述语言模拟pci数据接口的数据传输过程。-PCI simulation with FPGA, using the verilog hardware describing language to simulate data transfer processes on pci data interface.
QAM
- 16qam调制器的FPGA实现。使用Verilog实现全数字16-QAM调制器。-16qam Modulator FPGA. Use Verilog for full digital 16-QAM modulator.
Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
FPGA-DM9000A
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A for Verilog realization of Ethernet data sent and received
fpgajpeg
- fpga实现图像的压缩，适合初学者，很快了解图像压缩和verilog-fpga to achieve image compression, suitable for beginners, will soon understand the image compression and verilog
1602LCD-Verilog
- 用FPGA控制在LCD1602上显示一段字符串。可以对LCD1602的控制有更深的了解-Using FPGA to control the LCD1602 display a string. LCD1602 can have a better understanding of the control