搜索资源列表
verilog_usbblaster
- 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机
rtl
- JTAG design verilog code.
BiDirectionalCell
- verilog 实现的 jtag TAP , 转自 opencore.com, 已通过验证
ControlCell
- verilog 实现的 jtag TAP , 转自 opencore.com, 已通过验证
InputCell
- verilog 实现的 jtag TAP , 转自 opencore.com, 已通过验证
OutputCell
- verilog 实现的 jtag TAP , 转自 opencore.com, 已通过验证
USB_jtag
- 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。
TAP3
- JTAG TAP Statemachine verilog code
JTAGsoftcoredesignandsimulation
- 关于jtag软核设计与仿真的资料 利用verilog实现,并对仿真进行了说明-Jtag soft on information design and simulation using verilog implementation, and simulation are described
core
- OpenOCD内部Jtag层核心代码。OpenOCD可以使用户通过C代码仿真模拟Verilog-core of OPENOCD s JTAG
jtag_master_latest.tar
- jtag 主机,根据jtag 标准协议编写的verilog代码-the jtag host, according to the jtag standard agreement prepared by the verilog code
11061101469955
- This a 8051CPU core with Jtag, inclue all source code by verilog.-This is a 8051CPU core with Jtag, inclue all source code by verilog.
tap_controller
- JTAG tap controller, used for DFT(JTAG tap controller verilog version)