搜索资源列表
ClockGenerator
- Verilog code for a programmable clock generator
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
dds_generater
- 波形发生器,可以生成正弦波、三角波、方波、锯齿波;可以选择输出频率和幅度,基于DDS设计,verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
CCD_frequency_generator
- CCD工业相机六路频率发生器,VHDL语言实现,非Verilog HDL-CCD industrial camera image capture six-way frequency generator, VHDL language, non Verilog HDL.
DDS
- 基于FPGA,Verilog语言编写的DDS信号发生器,可生成方波、正玄波,三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
singnt
- 基于verilog的正弦发生器,可以产生正弦信号-Based verilog sine generator,Can produce a sinusoidal signal
ETH_GEN_CHK
- Ethernet packet generator and check (verilog),for Ethernet design purpose!
dds
- 这是一个用Verilog语言实现的一个数字信号产生器算法-This is a use Verilog language implementation of a digital signal generator is presented
FPGA_phase_lock_demodulation
- FPGA 用Verilog语言实现数字锁相解调系统,包含了正交的DDS函数发生器和相应的AD驱动-FPGA digital demodulation system in Verilog lock, comprising a DDS orthogonal function generator and driving the corresponding AD
PUF_TRNG
- this a verilog code of true random number generator using butterfly puf-this is a verilog code of true random number generator using butterfly puf
dds_synthesizer
- Verilog编写的基于DDS的信号发生器,频率可变。(Verilog prepared by the DDS-based signal generator, the frequency variable.)
DDS
- 描述了verilog实现的DDS信号发生器,可以经过FPGA验证,包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证,可以实现信号发生器的基本功能。希望大家珍惜,并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be
ahb_system_generator_latest.tar
- amba ahb master generator by using verilog
random_num_gen
- 本人用verilog编写的随机数生成文件,经测试可用。(I am prepared to use verilog random number generator, the test is available.)
wave
- 使用verilog语言实现包括正弦波、余弦波、锯齿波的发生。(Verilog realization of waveform generator)