搜索资源列表
m序列
- Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
8bitsine
- 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
xljcq
- 关于序列发生器的verilog. 希望能帮大家。-sequence generator on the Verilog. Hope you can help.
wavegenerator_testbench
- 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
Verilog-HDL-based-signal-generator
- 应用Verilog进行编写四种波形发生的程序，并结合DE2板与DVCC实验板上的D/A转换器在示波器显示出波形。初步了解Verilog的编程及DE2板的应用，加强对其的实际应用操作能力。-Verilog waveform application process for the preparation of the four occurred, combined with D DE2 board and DVCC experimental board/A converter in the osci
sv code for ic
- System verilog code for generator class
Random-number-generator-verilog
- Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
Clock-generator
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置-.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings
verilog-sin
- FPGA开发sin波形，用verilog写的正弦波发生器。-FPGA development sin wave with verilog write sine wave generator
test_ADDA_sin
- 正弦信号发生器，ADDA转换，单片机编程，(Sinusoidal signal generator, ADDA conversion, microcontroller programming)
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
Sender
- verilog langurage to generate random numbers
四通道DDS信号发生器
- 四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
DDS
- 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来(Verilog realizes DDS Signal Generator)
pseudo_random
- 基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍(Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the
sincos
- 实现正余弦函数Verilog语言的生成...............(sine wave generator by using verilog)
mcode
- 附有m码产生verilog文件和测试文件，以及详细说明。读者可根据说明配置任意级m序列发生器(With M code, Verilog files and test files are produced and detailed. The reader can configure an arbitrary m sequence generator according to the instructions)
Verilog-Generator-of-Neural-Networks
- 利用DE0nano开发板实现了对用的卷积神经网络(The CNN algorithm is implemented.based FPGA)
verilog实现dds
- 基于FPGA实现信号发生器的的功能，较好的参考资料。(The function of signal generator is realized based on FPGA, which is a good reference.)