搜索资源列表
sequencecontroller
- this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
pseudo-randomcodegenerator
- VERILOG语言编写的伪随机码产生器，可以ISE中编绎调试-VERILOG language of pseudo-random code generator, you can unravel ISE in debugging code
VGA
- VGA彩条信号发生器，使用Verilog编写-VGA color bar generator, written using the Verilog
tr_seq_gen
- sequence generator in verilog
fir_gen
- finite impulse response generator verilog code
DDS_verilog
- 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
DDS_single
- 基于FPGA的单路DDS函数发生器的实现 ，语言为Verilog-FPGA-based single-channel DDS function generator implementation language for Verilog
m-xulie
- 频率可步进M序列发生器 从10K 到100K ,步进为10K VERILOG编写-M-sequence generator frequency step from 10K to 100K, the preparation step for the 10K VERILOG
VGAverilog
- Simple vga generator in verilog
MSequenceGenerator
- 5位的M序列发生器，verilog代码实现。5次本原多项式采用f(x)=x^5+x^2+1-5 of the M-sequence generator, verilog code. 5 using a primitive polynomial f (x) = x ^ 5+ x ^ 2+1
Hamming_Encoder
- (7,4)Hammming码编码器，verilog代码实现。生成矩阵为G=[1,0,0,0 0,1,0,0 0,0,1,0 0,0,0,1 1,1,1,0 0,1,1,1 1,1,0,1]-(7,4) Hammming Encoder, verilog code. Generator matrix is G = [1,0,0,0 0,1,0,0 0,0,1,0 0,0,0,1 1,1,1,0 0,1, 1,1 1,1,0,1]
m_ca7
- verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。-CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.
filter
- Digital filter 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
obnar1
- Digital detector (a-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
obnar3
- Digital detector (b-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
lfsr
- simple PRBS generator using verilog hdl
cordic
- 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
dds1
- 用ALTERA 公司的fpga芯片，编程语言是VerilogHDL,实现DDS数字信号发生器，可以产生正弦信号，三角信号，矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
xinhao
- 基于verilog的数字信号产生器，包括三角波、方波、正弦波，频率可调。-Verilog-based digital signal generator, including a triangle wave, square wave, sine wave, frequency adjustable.
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star