搜索资源列表
Vending_Machine_using_verilog
- This file is full report. Vending machine of verilog HDL for soft drink are provide in this file.-Vending Machine is a soft drink dispensor machine that dispenses drink based on the amount deposited in the machine.
VerilogCh4
- VHDL and Verilog code referrals tools, EDA staff to be very helpful. vend machine
Advanced_Verilog_Design
- 以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, b
square-root
- Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware descr iption language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation avai
IEEE_standard_verilog
- 其中，Verilog硬件描述语言（HDL）的定义，在这个标准。 Verilog的HDL是一个正式的符号中的电子系统创建的各个阶段使用。因为它既是机读和人类可读的，它支持开发，验证，综合，硬件设计和测试，对数据通信的硬件设计，以及维修，改装和硬件采购。这个标准的主要对象是工具的实现者支持的语言和语言的高级用户。-The Verilog Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a
softdrink
- 自动售货机verilog源码,含找零功能，通过Modlesim,leonardo仿真，综合-Vending machine verilog source
zuyuan
- 这是一个实现有限状态机的verilog编程的程序-This is a realization of finite state machine programming procedures verilog
zhuangtaiji
- 检测姓名序列的状态机。使用VERILOG编写。平台是QuartusII9.1。Cyclone -Detection of sequence state machine name. Prepared using VERILOG. Platform is QuartusII9.1. Cyclone III
freg
- freg goes throught the road by finite machine(include Verilog code and test bench)
lsh
- 基于Verilog的状态机的流程图及源代码-Verilog state machine based on the flow chart and code
1602LCD
- 该程序是1602的verilog程序，该程序采用状态机编写-The program is 1602' s verilog program, the program prepared by the state machine
ywjc
- 采用状态机的方法实现移位寄存器，用Verilog HDL编写，已经通过验证。-The method uses the state machine implementation shift register, with write Verilog HDL has been verified.
zidongshouhuojisheji
- 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作，用有限状态机进行系统状态描述，自动售货机通电复位时，自动进入系统初始状态，本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品，输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the v
washer
- 本人用verilog HDL写的一个洗衣机工作流程。由于是第一次写，难免很多不足~多多指教.-well ,this is a verilog project which describes a washer machine.
data_check_hand_in
- 一个基于状态机的8位码流检测实现，Verilog语言，在ISE 10.1环境下编译通过。-A state machine-based 8-bit code stream detection to achieve, Verilog language, the ISE 10.1 environment compile.
FSM
- 有限状态机，用Verilog语言，执行正确，仿真通过。-Finite state machine, with the Verilog language, the implementation of the right, simulation pass.
washmachine
- 源码为洗衣机控制电路的Verilog代码实现，分六个模块实现，顶层模块有原理图实现-this code is for the control_circuit of machine in Verilog ,it is divided into six modules, the top-level is schematic
12.4Uart
- 最简单的verilog串口发送接收源代码,已经上机调试,请放心,直接使用-Simple transmit and receive serial verilog source code, has been on the machine commissioning, please rest assured, direct use
87361021ebook_verilog_fine_state_machine
- verilog finite state machine
rom_con_aa
- VERILOG 多线程控制程序，实现状态机控制ad采集-VERILOG multi-threaded control program, to achieve a state machine control ad acquisition