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CPU
- 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
fft1
- fft processor code working code in verilog--fft processor code working code in verilog-VVV
MIPS_Project
- Verilog Source File. MIPS Processor Pipelining
m.e-lab
- vhdl verilog code for alu operation pll,biy sliced processor
VLIW_uP_code
- VLIW processor code in verilog
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
Chapter-7
- 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
simple_CPU
- 通过利用verilog语言编写一个简单的处理器，并添加存储器功能-Verilog language through the use of a simple processor, and add the memory function
DataMemory
- datamemory code in verilog for pipeline processor
dp
- datapath code in verilog for pipeline processor
InstMemory
- instruction memory code in verilog for pipeline processor
multi_cycle_Verilog
- this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less th
-Elliptic
- We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coproc
32_bit_mpu
- I got my semester project on IMPLEMENTATION OF 32 BIT MIPS processor and implementation on XILINX spartan 3e.i made thys code on verilog and includes LCD interfacing with the kit
My_RASrm
- 流水线处理器的Verilog代码，结构简单，基本功能-the pipeline processor，code in Verilog
MIPS-multi-cycle-(Quarters-II--Verillig)
- Multi cycle MIPS processor verilog