当前位置：
首页 资源下载
搜索资源 - Verilog state machine
搜索资源列表
-
0下载：
本程序是用verilog 状态机编写的lcd1602的驱动程序，可以直接调用-The program is written in verilog lcd1602 state machine driver, you can directly call
-
-
0下载：
一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。-One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.
-
-
0下载：
verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
-
-
0下载：
一个基于verilog的iic协议的控制器，用状态机结构编写，可以将数据写入eeprom中，再读出来。-A protocol based on verilog for iic controller state machine structure with writing, data can be written to the eeprom, reading them out.
-
-
0下载：
状态机实现，通过简单的程序实现状态机，让你最快的掌握用VERIlog语言写的状态机-State machine implementation, through a simple procedure to implement state machines, allowing you the fastest master the language used to write state machine VERIlog
-
-
0下载：
用verilog语言实现自动售货机功能，其中使用了状态机来实现。-Vending machine using verilog language function, which uses a state machine.
-
-
0下载：
用VERILOG实现状态机，对状态机的理解很有帮助-Use VERILOG implementation state machine, the understanding of the state machine is very helpful
-
-
0下载：
verilog代码编写110100序列的序列检测器，用状态机实现，包括仿真测试代码-verilog coding sequence detector 110100 sequence state machine implementation, including simulation test code
-
-
0下载：
Verilog语言实现状态机的设计，实现的状态机总共有三种，均给出了具体的实现方案-Design and implementation of the state machine of the Verilog language, the state machine to achieve a total of three, were given a concrete implementation scheme
-
-
0下载：
verilog四状态状态机 带异步清零端和测试向量 mealy型状态机 很好用哦 -verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh well
-
-
0下载：
verilog编写的21点游戏，用状态机写的，A可以表示1也可以表示11.-verilog 21-point game, written by a state machine
-
-
0下载：
基于FPGA的洗衣机控制器 verilog语言 实现注水 脱水，正反转反复控制 状态机-FPGA-based controller verilog language washer water dehydration, reversing repeated control state machine
-
-
1下载：
I2C Master Code in Verilog using Finite State Machine.
-
-
0下载：
恒温控制器，由状态机连接到温度传感器，温度控制的控制。该代码是用verilog编写的恒温控制，在每个语句有一个中文的描述-Thermostat controller, controlled by a state machine connected to the temperature sensors, temperature control. The code is written in verilog thermostat control, after each statement has a
-
-
0下载：
基于Verilog的交通灯，包含分频器模块、计数模块以及控制模块。状态机编写-Verilog-based traffic lights, including the divider block, counting module and a control module. Write state machine
-
-
0下载：
状态机 多种状态的转换 verilog语言编写-Convert verilog language write state machine multiple states
-
-
0下载：
I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
-
-
0下载：
1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果；
2、设置有复位和启动/保持开关，要求
⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备；
⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。
3、采用Verilog HDL语言设计符合上述功能要求的控制电路。-1, with the state machine design A/
-
-
0下载：
在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
-
-
0下载：
序列检测，学习verilog三段式状态机的经典例程，modelsim仿真无误-Sequence Detection, three-state machine learning verilog classic routines, modelsim simulation is correct
-
«
1
2
...
5
6
7
8
9
1011
12
»
