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SDH开销的接收处理,要求:
1, A1和A2字节为帧头指示字节,A1为“11110110”,A2为“00101000”,连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机,从连续传输的SDH字节流中找出帧头。
2, E2字节为勤务话通道开销,用于公务联络语音通道,其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中,提取E2字节,并按照64K速率分别串行输出E2码流及时钟,其中64K时钟要求基本均匀。(输出端口包括串行数据和64K串行时钟)
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verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
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synopsis的有限状态机编码方法的文档。
针对synopsis的综合环境,根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。
FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the in
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如何用verilog语言写好状态机的不错的文档,希望对大家有所帮助-How to use Verilog state machine language to write good documentation, I hope all of you to help
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雷鸟车尾灯状态机,vhdl实现,对学习VHDL的同学有帮助。-Thunderbird taillights state machine, vhdl realize, the study has helped students VHDL.
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it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controlle
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输入输出控制的状态机,verilog HDL源码-Input and output control state machine, verilog HDL source
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状态机控制AD转换模块
该模块主要实现对MAX197的控制:根据设计需要对芯片进行初始化(包括写控制字选择输入电压值范围、选择通道以及工作模式),并把通道数送指示灯显示以及用键盘控制通道号(按一下,通道号加1,同时点亮相应的指示灯,循环使用个通道);控制状态机的工作时序,并置两次采集到的数据为12位数据输出,并经过锁存进程来锁存数据,最后从锁存器中把输出数据-The state machine controls AD and changes the module this module ma
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Quartus II工程压缩文件,是一个典型的基于FPGA的计价器工程项目,有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
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基于quartus的,状态机实现流水灯,verilog HDL语言编写-Quartus-based, the state machine to achieve water lights, verilog HDL language
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verilog编写的一个交通灯程序,利用状态机实现。压缩包内有说明文档,源代码及时序截图-verilog prepared a program of traffic lights, the use of state machine to achieve. Compressed packet, there are documentation, source code and timing Screenshots
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verilog实现的“状态机实现AD0809数模转换”。-verilog to achieve a " state machine to achieve AD0809 digital to analog conversion."
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verilog state machine coding style
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用VERILOG实现秒表的开发设计,(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理;(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发;(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface c
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用Verilog实现卷积码(2,1,2)的编码器,采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
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用状态机编写的FIR,verilog代码,已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
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1001 sequence detector in verilog code for mealy state machine
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基于Verilog的状态机的流程图及源代码-Verilog state machine based on the flow chart and code
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moore状态机实验verilog代码,我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
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控制左右两对灯一次点亮,用状态机实现,verolog语言编写-Control about two lit the lamp again with the state machine implementation, verolog language
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