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搜索资源 - Verilog state machine
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交通灯控制器的Verilog代码,采用了三段式的状态机描述,适合学习和练习,包括了验证代码-A Verilog code of Traffic light controller, using a three-stage state machine descr iption suitable for learning and practice, including the verification code
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verilog语言实现的iic协议通信,一段式状态机实现,结合按键和数码管,用来控制和显示数据-Verilog language the iic protocol communication, for some state machine implementation, buttons and digital tube, used to control and display data.
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verilog的按键消抖程序,利用状态机完成的-verilog the the key debounce program, the completion of the state machine
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autoseller machine is the main function of the code with the language of verilog. it is accomplished with the state machine.
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verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a
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自己编写的带有FIFO的UART串口发送模块,代码通过状态机实现,开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
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门锁 状态机 verilog 适用于digilent NEXYS2开发板,doorlock state machine
verilog applied to digilent NEXYS2 board
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基于MIPS思维方式,verilog语言,简单的cache 控制器设计,状态机共分4个状态,同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
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这是一个用verilog写的LED的控制代码,其中主要是利用状态机的形式实现的-This is a verilog the write LED control code, which is realized in the form of state machine
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verilog HDL语言编写的8位并串转换,使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ,can comprehense
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基于状态机编写的串口通信实验,编程语言是Verilog HDL,可发送八位数据,在Altera的EP4CE15F17C8芯片上验证成功。(与另一个发送256位不同的是这个代码比较突出状态机的使用)。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif
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精简指令集 CPU 通过仿真验证正确
(使用之前务必看readme文件,和结构图!)
1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。
2. 学习时务必先搞明白框图原理,和数据流动!!!
3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。
4. 理解数据总线,和地址总线。区分数据和地址。
5. 仔细调试,因为书中有很多小错误。
程序经过quartusii编译通过,另外经过modelsim仿真正确。-RISC
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利用有限状态机实现一般时序逻辑分析的方法;
进掌握用Verilog编写的有限状态机的标准模板-Finite state machine to achieve general sequential logic analysis method into the grasp of finite state machines using Verilog standard template
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一个简单的数字时钟Verilog仿真程序,60秒1分钟,60分一小时,24小时一天,265天一年。代码逻辑简化不含状态机,易理解。附激励文件可直接仿真。-A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies excluding state machine, easy to
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verilog编程状态机实战训练:1.本实例通过实现一个状态机来控制8个LED循环闪亮;
2. 工程在project文件夹里面;
3. 源文件和管脚分配在rtl文件夹里面;
4. 下载文件在download文件夹里面。-verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2
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用Verilog语言实现简单的16位状态机-Use Verilog language to design a 16 state machine
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通过verilog hdl语言实现对时序状态机的编写-By verilog hdl language for writing timing state machine
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用Verilog HDL 状态机实现的驱动数码管显示,是个很不错的模块,可以直接用-Using Verilog HDL state machine driven digital display, is a very good module, can be directly used
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本程序是用Verilog HDL 状态机编写的tlc549的驱动程序-This procedure is used to write Verilog HDL state machine driver tlc549
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本程序是用verilog 状态机编写的tlc5620的驱动程序,可以直接调用-The program is written in verilog tlc5620 state machine driver, you can directly call
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