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Verilog_EXAMPLE
- DesignWave 2005 8 Verilog Example -Design Wave Verilog Example
8bitsine
- 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
DDS_Power
- FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table thr
chengxing1
- 成型滤波器的verilog代码--Verilog source code for formatted wave filter.
dds(heli).rar
- DDS用verilog 实现，可以实现方波、正弦和三角,DDS using verilog realized, can be square wave, sinusoidal and triangular
vhdl
- 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware descr iption language phase accumulator, phase modulator, sine, square, triangle wave, the fo
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
VHDL_sin
- VHDL与Verilog示例（六） 8bit采样sine波形发生-VHDL and Verilog examples (f) 8bit sampling sine wave occurred
fb
- 占空比为1：1 的方波verilog程序，通过修改counter可以改变频率及占空比-1:1 duty cycle square wave of verilog procedures, counter can be changed by modifying the frequency and duty cycle
dds_var
- 自己写的一个简单的DDS控制器，此程序包包含完整的VERILOG写的程序，操作有点简单，输出正弦波，方波，锯齿波，通过键盘可以选择输出波形，与大家共享-To write a simple DDS controller, this package contains a complete program written in VERILOG, a bit simple to operate, the output sine wave, square wave, sawtooth, through t
square_syn
- 平方环载波同步法FPGA实现的verilog代码-square loop carrier wave syn
square
- This a verilog code for the generation of a square wave-This is a verilog code for the generation of a square wave..
sin
- 能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。(The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words.)
pulse
- 这是一个方波程序，在quartus平台编写，可以通过设置参数生成方波信号。(This is a square wave program, written in the quartus platform, you can generate square wave signals by setting parameters.)
Single_pwm
- 这是一个生成pwm波的程序，使用按键改变占空比的大小，通过增加按键的消抖程序能够精确控制占空比的变化。(This is a program to generate pwm wave, use the button to change the size of the duty cycle, by increasing the key of the shaking program can accurately control the duty cycle changes.)
sincos
- 实现正余弦函数Verilog语言的生成...............(sine wave generator by using verilog)
方波产生
- 设计一个方波产生电路，并进行功能验证和时序验证。(A square wave generation circuit is designed, and function verification and time series verification are carried out.)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
wave
- 使用verilog语言实现包括正弦波、余弦波、锯齿波的发生。(Verilog realization of waveform generator)
A4_Da_Top
- 利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(The simple oscilloscope is realized by using AD, DA and VGA peripherals. The DA peripheral sends sine wave to the AD peripheral, and the AD peripheral res