搜索资源列表
fenpin5_5
- Verilog 语言实现利用FPGA对输入方波实现5.5分频-the frequency of a rectangular wave is divided 5.5 using the FPGA
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
dds_generater
- 波形发生器,可以生成正弦波、三角波、方波、锯齿波;可以选择输出频率和幅度,基于DDS设计,verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
FPGA_WAVE
- FPGA VERILOG产生任意波形的信号-wave fpga verilog
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM,通过调用内部数据实现正弦波输出,开发环境quartusii , 语言verilog , 调试通过 , 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri
DDS
- 基于FPGA,Verilog语言编写的DDS信号发生器,可生成方波、正玄波,三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
pwm_generate_module
- verilog编写的,用按键控制PWM波占空比。可以定义死区,用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
8位数字显示的简易频率计
- (1)能够测试10HZ~10MHZ的方波信号; (2)电路输入的基准时钟为1HZ,要求测量值以8421BCD码形式输出; (3)系统有复位键; (4)采用分层次分模块的方法,用Verilog HDL进行设计,并对各个模块写出测试代码; (5)具体参照说明文档(包含源代码,仿真图,测试波形,详细的设计说明)(A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the ci
测pwm波占空比
- 基于Verilog的接受pwm波并且测量pwm波占空比(Measuring the duty cycle of PWM wave)
square_wave
- 使用FPGA的verilog语言生成方波调制波形(To generate square wave)
DACVERILOG
- DAC IC AD9708Driver code,use verilog hdl,Can output sine wave, cosine wave
DACAD9708
- DAC_AD9708的verilog hdl 代码,简单易懂,AD9708为top文件,需要自己配置只读存储器,输出正弦波。(DAC_AD9708 verilog HDL code, AD9708 for top file, need to configure read only memory, output sine wave.)
DDS30k
- 在quartus开发平台基于直接数字频率合成技术利用Verilog语言实现正弦信号和三角波信号发生(Verilog was used to generate sine and triangle wave signals based on direct digital frequency synthesis in quartus development platform.)
8bit-freqDetect
- 题目1:设计一个8位数字显示的简易频率计。要求: ①能够测试10Hz~10MHz方波信号; ②电路输入的基准时钟为1Hz,要求测量值以8421BCD码形式输出; ③系统有复位键; ④采用分层次分模块的方法,用Verilog HDL进行设计。 ⑤写出测试仿真程序(Topic 1: Design a simple frequency meter with 8 digits display. Requirement: It can test 10 Hz ~ 10 MHz square wave si