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verilog-code-style-specification
- 企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。-Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.
Verilog-HDL-Coding
- Motorala推荐的Verilog代码规范。对于VerilogHDL语言编写很有借鉴意义。-Motorala recommended Verilog code specifications. VerilogHDL language is useful for reference.
verilog-experience-for-beginners
- VerilogHDL语言的设计经验，适合初学者入门学习，包含了Verilog编写时需要注意的很多方面，很有参考价值。-VerilogHDL language of design experience, suitable for beginners to learn, including the need to pay attention when writing Verilog many aspects of great reference value.
PWM
- 使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。-The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..
FIFO
- 该代码为FIFO代码，编译环境为Quartus/Xilinx,语言为VerilogHDL-The code for the FIFO code, compile environment Quartus/Xilinx, language VerilogHDL
03_key_detect_1
- 该程序为按键防抖程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for key stabilization program, the compiler environment Quartus/Xilinx, use language VerilogHDL
07_number_mod
- 该程序为数码管程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for the digital program, the compiler environment Quartus/Xilinx, use language VerilogHDL
16_buzzer
- 该程序为蜂鸣器程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for the buzzer, compiler environment for Quartus/Xilinx, use language VerilogHDL
25_lcd_system
- 该程序为lcd程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for lcd, compiler environment for Quartus/Xilinx, use language VerilogHDL
HV528 driver with CPLD
- HV528 drive example with verilogHDL
crc
- 基于FPGA VerilogHDL 的crc的算法。-Crc algorithm based on FPGA VerilogHDL.
USBRead
- FPGA+USB通信程序VerilogHDL代码-the code of FPGA+USB communication in verilogHDL
VerilogHDL_module
- VerilogHDL那些事儿_建模篇和Verilog_HDL_那些事儿_时序篇v2是一个系列-VerilogHDL those things _ modeling and Verilog_HDL_ of those things _ timing is a series of V2
Reset
- 基于verilogHDL的异步复位，同步释放电路模块文件-Asynchronous reset, synchronous release circuit
RS_Encode_Decode
- RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。-RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.
Random_Derandom
- 通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。-Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.
Interleaver_Deinterleaver
- 通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。-Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.
veriloghdl
- Verilog VHDL study guide. good luck
basys3_timing
- 基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL-Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL
TLC5620
- TLC5620串行DA转换，verilogHDL语言-TLC5620 DA