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spi_write
- 基于veriloghdl语言的spi接口的写操作功能实现，程序经过了modelsim的仿真和上板的调试，功能正常。-the achieviation of spi interface based on the VerilogHdl language
APB_Servo_code_final
- test code by verilogHDL. SERVO MOTER operation code at FPGA. AHB and APB BUS Architecture.
21_flash_ddr_lcd
- flash与DDR3的程序，verilogHDL语言描述的程序-flash and ddr3 verilogHDL soft
11_ddr3_test
- ddr3的操作程序，用Veriloghdl写的FPGA程序-ddr3 veirloghdl operater xinlinx FPGA
fm
- FM调频的FPGA程序，用ALTERA的FPGA实现-FM altera fpga veriloghdl
fir-digital--lowpass-filter
- 基于verilogHDL硬件描述语言的fir数字低通滤波器的设计-fir digital lowpass filter design based on verilogHDL
dds
- verilogHDL中实现dds信号发生器的源码-VerilogHDL achieve dds signal generator source
Tlc5615_Dac
- 基于VerilogHDL的TLC5615控制模块的设计-Design of TLC5615 Based on FPGA
com_exec
- 基于VerilogHDL的串口控制模块的设计-Design of Serial Port Control Module Based on VerilogHDL
traffic
- 基于VerilogHDL的交通灯仿真的设计-Design of Traffic Light Simulation Based on VerilogHDL
music
- 基于VerilogHDL的音乐播放的设计-Design of Music Playing Based on VerilogHDL
paomadeng
- VerilogHDL实现跑马灯源码，开发环境：ISE14.7.板子测试Spartan3E - VerilogHDL实现跑马灯源码，开发环境：ISE14.7.板子测试Spartan3E VerilogHDL achieve marquee source code, development environment: ISE14.7. board test Spartan3E
dddddddd
- VerilogHDL秒表源程序，精确到0.01s，数码管6位显示。开发软件ISE14.7.-VerilogHDL stopwatch source, accurate to 0.01s, digital tube 6 bit display. Developing software ISE14.7.
VerilogHDL
- Samir Palnitkar-Verilog HDL_ a guide to digital design and synthesis-SunSoft Press (2003)
CRC5_CRC16_USB
- USB2.0数据包CRC 16，TOKEN令牌包是CRC5，VerilogHDL代码 多项式y=1+x^2+x^15+x^16; y=1+x^2+x^5; 只是串行1位的代码， 并行8位，16位没有上传(USB CRC 16 , VerilogHDL code polynomial(0_2_15_16); polynomial(0_2_5))
Verilog 150 classical examples
- FPGA VerilogHDL程序设计的150个经典实例，实用的FPGA学习与开发参考资料。(150 classical examples of FPGA VerilogHDL programming)
IIC_Host
- 用VerilogHDL语言编写的I2C配置程序(VerilogHDL I2C source code)
Zircon_Digital
- 多选一多路器，三人表决器，触发器，RS寄存器(Choose a road, three people vote, trigger, RS register)
chuankou
- 此文件是一个串口verilog程序，一次传输一个字节，使用quartus编写(This is a program that is written in Verilog language ,It is a Serial program ,You can transfer and return a byte data.)
不用IP核设计乘法器
- VerilogHDL语言实现 不用IP核设计乘法器。(VerilogHDL language, do not use IP core design multiplier.)