搜索资源列表
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘,采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
cla4
- verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位-verilog code4-bit carry look-ahead adderoutput [3:0] s// summationoutput cout// c
16weijiafaqi
- 本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.-This procedure is a full-adder based on the design of a 16-bit adder, using Verilog HDL language to describe.
myAddSub
- Verilog adder for alu develpment
select_adder
- implement of select adder with verilog
Adder_Verilog
- 对于Verilog初学者非常实用的代码,帮助了解许多常用的加法器-Very useful for beginners Verilog code to help understand the many commonly used adder
add_sub
- basu verilog codes for adder subtracor etc
FullAdderDesign
- Verilog Code For Full Adder
bitadder
- verilog code for 4 bit adder
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
add_16bits
- 這是16bits加法器,利用verilog程式撰寫-adder-19bts
full_adder_code_in_verilog
- full adder in verilog
fadd
- it is verilog code for floating point adder
ex1.v
- 用Verilog HDL 实现的4位二进制全加器。-4-bit full adder implemented with Verilog HDL
add
- 自己用verilog写的加法器,时序仿真已经通过-Their own written with verilog adder, timing simulation has been adopted
chengxu
- 加法器 比较器verilog hdl 等简单小程序 新手学习中 见谅-Adder comparator verilog hdl Adder comparator verilog hdl a small way as simple novice learning apologize
Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C
mul64
- 64位乘法器设计实验是我在科大的第一个课程设计,verilog程序的熟练掌握对于微电子专业的学生来讲是非常必要的,对于此次设计我也花费了很长时间。 本设计分为3个部分,即控制和(1)状态选择部分,(2)乘法器部分,(3)加法器部分。 以下我将按此顺序进行说明。需要指出的是,在实际设计中的顺序恰好是颠倒的,这与设计思路有关,在刚开始的时候由于对整体没有一个很好的把握就先选择最简单的一部分几加法器开始入手,然后就是乘法器,最后作乐一个状态控制电路将两部分联系起来。 -A 64-bit m
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.