搜索资源列表
half_adder
- 半加器 用verilog语言编写一个半加器,测试结果正确。-half adder
FPGA_Programming
- 介绍FPGA的基本结构、开发流程与Verilog HDL语言基础,并附有加法器、移位寄存器等代码的实现。-Introduce the basic structure of the FPGA development process, and Verilog HDL language foundation, along with the adder, shift register code.
multiplier
- 8 bits multiplier module in verilog a[7:0]*b[7:0]=c[8:0] // only use one adder
add32
- 加法器;32位;verilog hdl -Adder 32 Verilog hdl
Cverilogcodeo
- 包含了加法器、移位寄存器、时钟等等Verilog源代码。 -Contains the adder, shift register, clock, etc. Verilog source code.
my_half_add
- 基于FPGA的半加器源码,声明,有verilog编写的-FPGA-based half adder source, statement, written in verilog
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
float
- 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
carrylook4bit
- carry 4-bit adder program in verilog
d10-counter
- 十位加法器,用verilog语言编写,适用于verilog学习。-10-bit adder, using Verilog language, applicable in verilog learning.
add
- FPGA VERILOG 加法器,数码管显示-FPGA VERILOG the Adder, digital tube display
add_ded_module
- 使用Verilog语言编写的4位加减法器,经验证能在FPGA开发板上实现。-Verilog4 bit adder-subtractor.
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台,用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
full_add
- 这个是用verilog语言写的一个全加器的程序-This is to use verilog language to write a full adder program
ADD
- Verilog编写的Altera单精度加法器源码-Altera single precision adder source Verilog prepared
test
- the carry save adder program in verilog
xjwbwd
- 这个fpadd程序应用verilog语言,实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
code
- 32位全加器 使用verilog写的硬件描述语言,xilinx芯片上运行过-32bits full adder
ripplecarryadder
- ripple carry adder in verilog