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add_tree
- 加法树的源代码，是乘法和除法的基础，也即数字电路的verilog基础代码，已经仿真过，完全正确-Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
cla32
- verilog code for cla 32 bit adder
adder8_4
- 用Verilog HDL编写的8位加法器程序，加法器采用4级流水线的方式实现。-8-bit adder program written using Verilog HDL, the adder 4 pipeline.
twoBitAdder
- N-bit adder implemented in verilog
PROJECT1-20130414-20130512
- 16bit adder的verilog源代码和4bit的计数器源代码-source code for 16bit adder and 4bit counter
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
UDP
- 这是用Verilog HDL编写的程序 利用UDP方法实现四位加法器-This is written in Verilog HDL programs Use UDP method four adder
addr_rtl
- 利用Verilog HDL编写程序 利用assign语句实现加法器-Use Verilog HDL to write programs Using the assign statement adder
Adder12_2-6
- This an 12 bits adder in Verilog. it adds two 6 bit nibbles parallel.-This is an 12 bits adder in Verilog. it adds two 6 bit nibbles parallel.
Adder12_3-4
- This is an 12 bits adder in Verilog. it adds three 4 bit nibbles in parallel.
Adder12_4-3
- This an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.-This is an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.
project3_1
- 逐次进位加法器，HDl verilog语言编写，能在DE2上运行-Successive carry adder, HDl verilog language, able to run on the DE2
jianyijiafaqi
- 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
chaoqianjinweiliuweijiafaqi
- 六位加法器（逻辑门电路实现）verilog 语言编写-6 bit Adder
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器，除法器的设计-Achieved through verilog hdl adder multiplier, divider design
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略，∑-Δ DAC的内部仅由2个10位的二进制加法器，1个10位的锁存器和一个D触发器组成，用FPGA实现时只需耗费极少的逻辑资源，即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
lab7
- 利用verilog语言设计32位进位选择加法器。实现高速计算功能。-Use verilog language design 32 carry select adder. High-speed computing.
modelsimPdebussy-batch-processing
- 内容包括采用Windows批处理方式高效执行Verilog仿真验证的方法，采用Modelsim+debussy联合仿真，里面包含一个加法器实例，批处理文件，仿真指令等。-Included with Windows batch efficient implementation of Verilog simulation method, using Modelsim+debussy co-simulation, which contains an example of an adder, batch
fpaddmisc-(1)
- VERILOG CODE FOR FLOating point adder
Rashed
- simple Adder in verilog (xilinx)