搜索资源列表
half
- This is a verilog half adder code
counter
- 采用VERIlOG HDL语言设计的一个加法器项目，简单可靠，并把其中测试平台程序加入其中-VERIlOG HDL language designed using an adder project, simple, reliable, and to join the program in which the test platform
FASwitch
- Full Adder Design in Switch level Modelling using Verilog
RCA
- ripple carry adder design using verilog
Verilog_100exaples
- Verilog的100个经典设计实例，包括交通灯的设计代码，智能时钟的设计代码，各种加法器。乘法器的设计代码-100 classic Verilog design examples, including the traffic light design code, intelligent clock design code, a variety of adder. Multiplier code
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
claadder
- 4 Bit Carry Look Ahead Adder in Verilog.
bcdadd
- 4-Bit BCD Adder in Verilog
Lab9_adder4a
- 4位加法器的设计与实现.4位加法器框图，本实验中用Verilog语句来描述.nexy3.-With the implementation of.4 bit adder block design of 4 bit adder, the Verilog statement in this experiment to describe.Nexy3
add
- Verilog 语言 加法器仿真调试过，没有任何问题 很简单的FPGA入门。-Verilog adder
adder8
- 8位全加器，Verilog硬件语言源代码。最基础的加法器。-8-bit carry-ripple adder， the basic adder。Achieved by verilog source code.
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
flow_proc
- 流水线结构是在逻辑很复杂的情况下使用，通过分栈，把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。最形象的实例就是位宽较大的加法器。此程序就是verilog的实现 -In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation
fullAdder32
- 阵列加法器,实现加法功能，快速加法的功能，verilog代码-Array adder adding function to achieve rapid addition of features, verilog code
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.
adder16.v
- 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
addercs16.v
- 这是自己写的 16 bits carry select adder 的verilog的代码，如果有用fell free to download-It is 16 bits verilog write their own code to carry select adder, if a useful fell free to download
day5_fastadder
- this is an implementation of fast adder algorithm in verilog.
Sum
- 实现加法器功能的简单verilog代码，可以为初学者提供学习。-Achieve a simple verilog adder function code can provide learning for the beginners.