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add
- 加法器的verilog代码希望对需要的人起一定的参考-Adder verilog code hope for those who need to play a certain reference
code
- 32bits流水线加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through
daima
- 32bits进位选择加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits carry select adder verilog language, xilinx chip run through
daima
- 32bits提前进位加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits advance carry adder verilog language, xilinx chip run through
code
- 32bits补码加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits complement adder verilog language, xilinx chip run through
4bit-parallel-adder
- The program contains verilog code for 4bit parallel adder
Carry_Select_Adder_Verilog
- 进位选择加法器，verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.
adder16_2
- １６位２级流水线加法器的ｖｅｒｉｌｏｇ设计-16 2 pipeline adder Verilog design
Chapter15-Adder
- 书籍《精通Verilog HDL语言编程》中第15章的程序实例代码，是关于常用加法器的设计的，对于初学者有一定的帮助-Books "Proficient in Verilog HDL language programming" in Chapter 15 of the procedure code, common adder design have some help for beginners
adder
- 这是一个最简单的四位的全加器设计，由两个半加器构成，采用的是VERILOG的算法级和门级描述的。-This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descr iptions.
full
- This a full adder verilog code-This is a full adder verilog code
Carry-Select-Adder
- verilog code for carry select adder
4bit-parallel-adder
- The program contains verilog code for 4bit parallel adder
aadd4
- verilog 描述的超前进位加法器，速度较快，可综合-lookahead adder verilog descr iption, faster, can be integrated
src
- 32位加法器,verilog HDL，初级用，-32-bit adder, verilog HDL
verilog
- 数字信号处理的FPGA实现 第三版 verliog 从简单的加法器 到 现代滤波器-FPGA implementation of digital signal processing third edition verliog from simple adder to modern filter
32ADD
- 32位超前进位加法器，verilog hdl代码实现，包含源程序-32 lookahead adder, verilog hdl code, including source code
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
fulladder-using-half-adder
- half adder full adder using half adder in verilog