搜索资源列表
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
BKA264
- Verilog - Brent-Kung Adder 32-bits
CSA464
- Verilog - Combinational part of Carry-Save adder, 4 operands 64-bits
HCA464
- Verilog - Descr iption of a 4 operand 64-bit Hans-Carlson adder
add
- verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)
BCDadder
- cource code for BCD adder in verilog language
常用加法器设计
- 采用Verilog设计的几种常用加法器。(several adder designed by Verilog)
4bitadderkoggestone
- Kogge stone adder implementation in verilog
Task1_WithCLK
- half adder with verilog coding for
Task1
- verilog code for a full adder
lab1
- 用半加器搭建全加器 使用Verilog语言(Using a half adder to build a full adder, using the Verilog language)
ModelSim
- Implementing a full adder in ModelSim by using Verilog Language
add
- 一个用quartus原理图输入的全加器，(A full adder with quartus schematic input,)
CLA代码
- 计数器跳跃进位加法器CLA代码，加法器计数器(adder with four 8-bit groups. 8-bit adder will have two 4-bit groups.)
4Bit超前进位加法器门级电路设计与仿真
- 用门级网表的方法对4Bit超前进位加法器门级电路连接关系用verilog语言进行描述(The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist)
code
- adder 18b trong chuong trinh verilog
adder_4bits
- 实现四位先行加法器的功能以及测试代码，其中adder_4bits.v为模块代码，adder_4bits—_tb.v为测试代码。还附加 部分其他加法器测试代码(Implement the function of four bit first adder and test code)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)